[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220919143627.13803-10-vidyas@nvidia.com>
Date: Mon, 19 Sep 2022 20:06:27 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
<bhelgaas@...gle.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <kishon@...com>, <vkoul@...nel.org>,
<mani@...nel.org>, <Sergey.Semin@...kalelectronics.ru>,
<ffclaire1224@...il.com>
CC: <linux-pci@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
<sagar.tv@...il.com>
Subject: [PATCH V1 9/9] PCI: tegra194: Calibrate P2U for endpoint mode
Calibrate P2U for endpoint to request UPHY PLL rate change to Gen1 during
initialization.
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 35d9c3ac3028..67dd97f3cd6e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1078,6 +1078,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
ret = phy_power_on(pcie->phys[i]);
if (ret < 0)
goto phy_exit;
+
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+ phy_calibrate(pcie->phys[i]);
}
return 0;
--
2.17.1
Powered by blists - more mailing lists