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Message-ID: <CAOtMz3NY=iGf8yUwv_u1y6ke1taqi1-rcZOSZdj+n8a4+JJ3BQ@mail.gmail.com>
Date: Tue, 20 Sep 2022 18:27:41 +0200
From: Jan Dąbroś <jsd@...ihalf.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
jarkko.nikula@...ux.intel.com, wsa@...nel.org,
rrangel@...omium.org, upstream@...ihalf.com,
mario.limonciello@....com
Subject: Re: [PATCH -next 1/2] i2c: designware: Switch from using MMIO access
to SMN access
Hi Andy,
pon., 19 wrz 2022 o 15:59 Andy Shevchenko
<andriy.shevchenko@...ux.intel.com> napisał(a):
>
> On Fri, Sep 16, 2022 at 03:18:53PM +0200, Jan Dabros wrote:
> > Due to a change in silicon compared to Cezanne, in future revisions MSR
> > access can't be used to get the base address of the PSP MMIO region that
> > contains the PSP mailbox interface.
> >
> > Modify driver to use SMN access also for Cezanne platforms (it is
> > working there) in order to simplify codebase when adding support for new
> > SoC versions.
> >
> > Export amd_cache_northbridges() which was unexported by
>
> > e1907d3: "x86/amd_nb: Unexport amd_cache_northbridges()"
>
> Please, use standard format of referring to the commits in the history
> (basically the same as for Fixes tags).
Sure.
>
> > since function which registers i2c-designware-platdrv is a
> > subsys_initcall that is executed before fs_initcall (when enumeration of
> > NB descriptors occurs). Thus in order to use SMN accesses it's necessary
> > to explicitly call amd_cache_northrbidges() from within this driver.
>
> Also it doesn't clarify if this commit a full revert of that (rebased for
> new kernel versions) or partial or functional?
This is a partial revert, I will mention this in the commit msg.
Best Regards,
Jan
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