linux-kernel - RE: [BUG] ls1046a: eDMA does not transfer data from I2C

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 20 Sep 2022 22:58:53 +0000
From:   Leo Li <leoyang.li@....com>
To:     Robin Murphy <robin.murphy@....com>,
        Sean Anderson <sean.anderson@...o.com>,
        Oleksij Rempel <linux@...pel-privat.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        "linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Vinod Koul <vkoul@...nel.org>,
        "dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>
CC:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        Christian König <christian.koenig@....com>,
        "linaro-mm-sig@...ts.linaro.org" <linaro-mm-sig@...ts.linaro.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        Joy Zou <joy.zou@....com>,
        "linux-media@...r.kernel.org" <linux-media@...r.kernel.org>
Subject: RE: [BUG] ls1046a: eDMA does not transfer data from I2C

> >
> > Despite the DMA completing successfully, no data was copied into the
> > buffer, leaving the original (now junk) contents. I probed the I2C bus
> > with an oscilloscope, and I verified that the transfer did indeed occur.
> > The timing between submission and completion seems reasonable for the
> > bus speed (50 kHz for whatever reason).
> >
> > I had a look over the I2C driver, and nothing looked obviously
> > incorrect. If anyone has ideas on what to try, I'm more than willing.
> 
> Is the DMA controller cache-coherent? I see the mainline LS1046A DT doesn't
> have a "dma-coherent" property for it, but the behaviour is entirely
> consistent with that being wrong - dma_map_single() cleans the cache,
> coherent DMA write hits the still-present cache lines,

So the coherent DMA write only gets data into the cache not also the DRAM?  Otherwise a read back would get the updated data too.

- Leo

> dma_unmap_single() invalidates the cache, and boom, the data is gone and
> you read back the previous content of the buffer that was cleaned out to
> DRAM beforehand.
> 
> Robin.
> 
> > --Sean