| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <202209201539.wghiUnB8-lkp@intel.com>
Date: Tue, 20 Sep 2022 15:39:51 +0800
From: kernel test robot <lkp@...el.com>
To: Tomer Maimon <tmaimon77@...il.com>, mturquette@...libre.com,
sboyd@...nel.org, avifishman70@...il.com, tali.perry1@...il.com,
joel@....id.au, venture@...gle.com, yuenn@...gle.com,
benjaminfair@...gle.com
Cc: kbuild-all@...ts.01.org, openbmc@...ts.ozlabs.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Tomer Maimon <tmaimon77@...il.com>
Subject: Re: [PATCH v10 1/1] clk: npcm8xx: add clock controller
Hi Tomer,
I love your patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on linus/master v6.0-rc6 next-20220919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Tomer-Maimon/Introduce-Nuvoton-Arbel-NPCM8XX-BMC-SoC/20220920-020013
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: s390-allyesconfig
compiler: s390-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/277a024d7abc4285dc553dea240bb5ac37cf8d33
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Tomer-Maimon/Introduce-Nuvoton-Arbel-NPCM8XX-BMC-SoC/20220920-020013
git checkout 277a024d7abc4285dc553dea240bb5ac37cf8d33
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash drivers/clk/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
drivers/clk/clk-npcm8xx.c: In function 'npcm8xx_clk_probe':
>> drivers/clk/clk-npcm8xx.c:464:52: warning: passing argument 2 of 'npcm8xx_clk_register_pll' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
464 | hw = npcm8xx_clk_register_pll(dev, pll_clk, clk_base);
| ^~~~~~~
drivers/clk/clk-npcm8xx.c:80:70: note: expected 'struct npcm8xx_clk_pll *' but argument is of type 'const struct npcm8xx_clk_pll *'
80 | npcm8xx_clk_register_pll(struct device *dev, struct npcm8xx_clk_pll *pll,
| ~~~~~~~~~~~~~~~~~~~~~~~~^~~
vim +464 drivers/clk/clk-npcm8xx.c
426
427 static int npcm8xx_clk_probe(struct platform_device *pdev)
428 {
429 struct clk_hw_onecell_data *npcm8xx_clk_data;
430 struct device *dev = &pdev->dev;
431 void __iomem *clk_base;
432 struct resource *res;
433 struct clk_hw *hw;
434 int i, err;
435
436 npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
437 NPCM8XX_NUM_CLOCKS),
438 GFP_KERNEL);
439 if (!npcm8xx_clk_data)
440 return -ENOMEM;
441
442 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443 clk_base = devm_ioremap(dev, res->start, resource_size(res));
444 if (!clk_base) {
445 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
446 return -ENOMEM;
447 }
448
449 npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
450
451 for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
452 npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
453
454 /* Reference 25MHz clock */
455 hw = clk_hw_register_fixed_rate(dev, "refclk", NULL, 0, NPCM8XX_REF_CLK);
456 if (IS_ERR(hw))
457 return PTR_ERR(hw);
458 npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK] = hw;
459
460 /* Register plls */
461 for (i = 0; i < ARRAY_SIZE(npcm8xx_pll_clks); i++) {
462 const struct npcm8xx_clk_pll *pll_clk = &npcm8xx_pll_clks[i];
463
> 464 hw = npcm8xx_clk_register_pll(dev, pll_clk, clk_base);
465 if (IS_ERR(hw)) {
466 dev_err(dev, "npcm8xx_clk: Can't register pll\n");
467 goto unregister_refclk;
468 }
469 }
470
471 /* Register fixed dividers */
472 hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL1_DIV2,
473 NPCM8XX_CLK_S_PLL1, 0, 1, 2);
474 if (IS_ERR(hw)) {
475 dev_err(dev, "npcm8xx_clk: Can't register fixed div\n");
476 goto unregister_refclk;
477 }
478
479 hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL2_DIV2,
480 NPCM8XX_CLK_S_PLL2, 0, 1, 2);
481 if (IS_ERR(hw)) {
482 dev_err(dev, "npcm8xx_clk: Can't register pll div2\n");
483 goto unregister_refclk;
484 }
485
486 hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PRE_CLK,
487 NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
488 if (IS_ERR(hw)) {
489 dev_err(dev, "npcm8xx_clk: Can't register ckclk div2\n");
490 goto unregister_refclk;
491 }
492
493 hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_AXI,
494 NPCM8XX_CLK_S_TH, 0, 1, 2);
495 if (IS_ERR(hw)) {
496 dev_err(dev, "npcm8xx_clk: Can't register axi div2\n");
497 goto unregister_refclk;
498 }
499
500 hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_ATB,
501 NPCM8XX_CLK_S_AXI, 0, 1, 2);
502 if (IS_ERR(hw)) {
503 dev_err(dev, "npcm8xx_clk: Can't register atb div2\n");
504 goto unregister_refclk;
505 }
506
507 /* Register clock dividers specified in npcm8xx_divs */
508 for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
509 const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
510
511 hw = devm_clk_hw_register_divider(dev, div_data->name,
512 div_data->parent_name,
513 div_data->flags,
514 clk_base + div_data->reg,
515 div_data->shift,
516 div_data->width,
517 div_data->clk_divider_flags,
518 &npcm8xx_clk_lock);
519 if (IS_ERR(hw)) {
520 dev_err(dev, "npcm8xx_clk: Can't register div table\n");
521 goto unregister_refclk;
522 }
523
524 if (div_data->onecell_idx >= 0)
525 npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
526 }
527
528 /* Register muxes */
529 for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
530 const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
531
532 hw = clk_hw_register_mux_table(dev, mux_data->name,
533 mux_data->parent_names,
534 mux_data->num_parents,
535 mux_data->flags,
536 clk_base + NPCM8XX_CLKSEL,
537 mux_data->shift,
538 mux_data->mask, 0,
539 mux_data->table,
540 &npcm8xx_clk_lock);
541
542 if (IS_ERR(hw)) {
543 dev_err(dev, "npcm8xx_clk: Can't register mux\n");
544 goto err_mux_clk;
545 }
546
547 if (mux_data->onecell_idx >= 0)
548 npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
549 }
550
551 err = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
552 npcm8xx_clk_data);
553 if (err) {
554 dev_err(dev, "unable to add clk provider\n");
555 hw = ERR_PTR(err);
556 goto err_mux_clk;
557 }
558
559 return err;
560
561 err_mux_clk:
562 while (i--) {
563 if (npcm8xx_muxes[i].onecell_idx >= 0)
564 clk_hw_unregister_mux(npcm8xx_clk_data->hws[npcm8xx_muxes[i].onecell_idx]);
565 }
566 unregister_refclk:
567 clk_hw_unregister(npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK]);
568 return PTR_ERR(hw);
569 }
570
--
0-DAY CI Kernel Test Service
https://01.org/lkp
View attachment "config" of type "text/plain" (305665 bytes)
Powered by blists - more mailing lists