linux-kernel - Re: [PATCH v3 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value

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Message-Id: <20220920081615.598292-1-miquel.raynal@bootlin.com>
Date:   Tue, 20 Sep 2022 10:16:15 +0200
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org
Cc:     Miquel Raynal <miquel.raynal@...tlin.com>,
        linux-kernel@...r.kernel.org, tlanger@...linear.com,
        rtanwar@...linear.com, richard@....at, vigneshr@...com,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v3 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value

On Sat, 2022-07-02 at 23:12:21 UTC, Martin Blumenstingl wrote:
> The Intel LGM NAND IP only supports two chip selects: There's only two
> CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
> according to the dt-bindings.
> 
> Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
> Acked-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel