linux-kernel - Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation

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Message-ID: <CAP6Zq1iwW6HvvfM684VLG0ZT-0OLKT0udW4bHxsZsTMEypo2sg@mail.gmail.com>
Date:   Tue, 20 Sep 2022 11:32:06 +0300
From:   Tomer Maimon <tmaimon77@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Rob Herring <robh@...nel.org>,
        Avi Fishman <avifishman70@...il.com>,
        Tali Perry <tali.perry1@...il.com>,
        Joel Stanley <joel@....id.au>,
        Patrick Venture <venture@...gle.com>,
        Nancy Yuen <yuenn@...gle.com>,
        Benjamin Fair <benjaminfair@...gle.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        zhengbin13@...wei.com, OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation

On Tue, 20 Sept 2022 at 11:21, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 20/09/2022 09:59, Tomer Maimon wrote:
> >>>>>>> +      pinctrl: pinctrl@...00000 {
> >>>>>>> +        compatible = "nuvoton,npcm845-pinctrl";
> >>>>>>> +        ranges = <0x0 0x0 0xf0010000 0x8000>;
> >>>>>>> +        #address-cells = <1>;
> >>>>>>> +        #size-cells = <1>;
> >>>>>>> +        nuvoton,sysgcr = <&gcr>;
> >>>>>>> +
> >>>>>>> +        gpio0: gpio@...10000 {
> >>>>>>
> >>>>>> gpio@0
> >>>>>>
> >>>>>> Is this really a child block of the pinctrl? Doesn't really look like it
> >>>>>> based on addressess. Where are the pinctrl registers? In the sysgcr? If
> >>>>>> so, then pinctrl should be a child of it. But that doesn't really work
> >>>>>> too well with gpio child nodes...
> >>>>> the pin controller mux is handled by sysgcr this is why the sysgcr in
> >>>>> the mother node,
> >>>>> and the pin configuration are handled by the GPIO registers.  each
> >>>>> GPIO bank (child) contains 32 GPIO.
> >>>>> this is why the GPIO is the child node.
> >>>>
> >>>> Then maybe pinctrl should be the sysgcr and expose regmap for other devices?
> >>> The pin controller using the sysgcr to handle the pinmux, this is why
> >>> the sysgcr is in the mother node, is it problematic?
> >>
> >> You said pin-controller mux registers are in sysgcr, so it should not be
> >> used via syscon.
> > Sorry but maybe I missed something.
> > the sysgcr is used for miscellaneous features and not only for the pin
> > controller mux, this is why it used syscon and defined in the dtsi:
> >                 gcr: system-controller@...00000 {
> >                         compatible = "nuvoton,npcm845-gcr", "syscon";
> >                         reg = <0x0 0xf0800000 0x0 0x1000>;
> >                 };
> >>
> >> Please provide address map description to convince us that this is
> >> correct HW representation.
> > GCR (sysgcr) registers 0xf0800000-0xf0801000 - used for miscellaneous
> > features, not only pin mux.
> > GPIO0 0xf0010000-0xf0011000
> > GPIO1 0xf0011000-0xf0012000
> > ...
> > GPIO7 0xf0017000-0xf0018000
> >>
>
> Then why your pinctrl is in sysgcr IO range? (pinctrl@...00000)
you suggest using pinctrl@0 or pinctrl@...10000 and not
pinctrl@...00000 because 0xf0800000 is the GCR address that serve
miscellaneous features and not only pinmux controller ?
>
> Your map looks quite different from what you described in example.
>
> Best regards,
> Krzysztof

Best regards,

Tomer