linux-kernel - Re: [RESEND PATCH v2] mailbox: mtk-cmdq: fix gce timeout issue

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <afa996b6-ee13-5add-9248-9339aa0beb02@collabora.com>
Date:   Tue, 20 Sep 2022 10:48:56 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Yongqiang Niu <yongqiang.niu@...iatek.com>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>
Cc:     Jassi Brar <jassisinghbrar@...il.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Hsin-Yi Wang <hsinyi@...omium.org>
Subject: Re: [RESEND PATCH v2] mailbox: mtk-cmdq: fix gce timeout issue

Il 19/09/22 09:12, Yongqiang Niu ha scritto:
> 1. enable gce ddr enable(gce reigster offset 0x48, bit 16 to 18) when gce work,
> and disable gce ddr enable when gce work job done
> 2. split cmdq clk enable/disable api, and control gce ddr enable/disable
> in clk enable/disable function to make sure it could protect when cmdq
> is multiple used by display and mdp
> 
> this is only for some SOC which has flag "control_by_sw".
> for this kind of gce, there is a handshake flow between gce and ddr
> hardware,
> if not set ddr enable flag of gce, ddr will fall into idle mode,
> then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
> 
> ddr problem is a special case.
> when test suspend/resume case, gce sometimes will pull ddr, and ddr can
> not go to suspend.
> if we set gce register 0x48 to 0x7, will fix this gce pull ddr issue,
> as you have referred [1] and [2] (8192 and 8195)
> but for mt8186, the gce is more special, except setting of [1] and [2],
> we need add more setting set gce register 0x48 to (0x7 << 16 | 0x7)
> when gce working to make sure gce could process all instructions ok.
> this case just need normal bootup, if we not set this, display cmdq
> task will timeout, and chrome homescreen will always black screen.
> 
> and with this patch, we have done these test on mt8186:
> 1.suspend/resume
> 2.boot up to home screen
> 3.playback video with youtube.
> 
> suspend issue is special gce hardware issue, gce client  driver
> command already process done, but gce still pull ddr.
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> ---
>   drivers/mailbox/mtk-cmdq-mailbox.c | 66 +++++++++++++++++++++++++++---
>   1 file changed, 61 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..3a1b11de84be 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -80,16 +80,60 @@ struct cmdq {
>   	bool			suspended;
>   	u8			shift_pa;
>   	bool			control_by_sw;
> +	bool			sw_ddr_en;
>   	u32			gce_num;
> +	atomic_t		usage;
> +	spinlock_t		lock;
>   };
>   
>   struct gce_plat {
>   	u32 thread_nr;
>   	u8 shift;
>   	bool control_by_sw;
> +	bool sw_ddr_en;
>   	u32 gce_num;
>   };
>   
> +static s32 cmdq_clk_enable(struct cmdq *cmdq)
> +{
> +	s32 usage, ret;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&cmdq->lock, flags);
> +
> +	usage = atomic_inc_return(&cmdq->usage);
> +
> +	ret = clk_bulk_enable(cmdq->gce_num, cmdq->clocks);
> +	if (usage <= 0 || ret < 0) {
> +		dev_err(cmdq->mbox.dev, "ref count %d ret %d suspend %d\n",
> +			usage, ret, cmdq->suspended);
> +	} else if (usage == 1) {
> +		if (cmdq->sw_ddr_en)
> +			writel((0x7 << 16) + 0x7, cmdq->base + GCE_GCTL_VALUE);

Can this be used on MT8192/MT8195?
If yes, you can avoid adding that sw_ddr_en, as you would be able to simply
use `control_by_sw`, which already seems to be doing most of what you're adding
here.

Also, I dislike all this locking: the point of having MTK CMDQ is to improve
performance (I know it's more than that, but there's no ISP upstream) and part
of that happens because locking is greatly reduced.

If you add it back up, we're losing part of the point.

Though, in this driver, we are already tracking the usage of the CMDQ threads
and, when there's no more usage, we're turning off the clocks: this is done
through the usage of `task_busy_list`, so you *do* have a way to avoid adding
more locks around.
Besides that, you could also add a clock notifier for the same, but since
the state is already tracked, I'd avoid using that.

Moreover, (7 << 16) == GENMASK(18, 16)

#define GCE_CMD_SOMETHING GENMASK(18, 16)

Regards,
Angelo