| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220920090038.15133-5-chunfeng.yun@mediatek.com>
Date: Tue, 20 Sep 2022 17:00:24 +0800
From: Chunfeng Yun <chunfeng.yun@...iatek.com>
To: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Vinod Koul <vkoul@...nel.org>
CC: Philipp Zabel <p.zabel@...gutronix.de>,
Chunfeng Yun <chunfeng.yun@...iatek.com>,
Kishon Vijay Abraham I <kishon@...com>,
Matthias Brugger <matthias.bgg@...il.com>,
<dri-devel@...ts.freedesktop.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Jitao Shi <jitao.shi@...iatek.com>,
Stanley Chu <stanley.chu@...iatek.com>
Subject: [PATCH 04/18] phy: mediatek: ufs: use common register access helpers
No need define private register access helpers, use common ones defined
in phy-mtk-io.h
Signed-off-by: Chunfeng Yun <chunfeng.yun@...iatek.com>
---
drivers/phy/mediatek/phy-mtk-ufs.c | 78 +++++++++++-------------------
1 file changed, 28 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
index a6af06941203..fc19e0fa8ed5 100644
--- a/drivers/phy/mediatek/phy-mtk-ufs.c
+++ b/drivers/phy/mediatek/phy-mtk-ufs.c
@@ -11,6 +11,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "phy-mtk-io.h"
+
/* mphy register and offsets */
#define MP_GLB_DIG_8C 0x008C
#define FRC_PLL_ISO_EN BIT(8)
@@ -39,34 +41,6 @@ struct ufs_mtk_phy {
struct clk_bulk_data clks[UFSPHY_CLKS_CNT];
};
-static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg)
-{
- return readl(phy->mmio + reg);
-}
-
-static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg)
-{
- writel(val, phy->mmio + reg);
-}
-
-static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
-{
- u32 val;
-
- val = mphy_readl(phy, reg);
- val |= bit;
- mphy_writel(phy, val, reg);
-}
-
-static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
-{
- u32 val;
-
- val = mphy_readl(phy, reg);
- val &= ~bit;
- mphy_writel(phy, val, reg);
-}
-
static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
{
return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy);
@@ -84,57 +58,61 @@ static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
{
+ void __iomem *mmio = phy->mmio;
+
/* release DA_MP_PLL_PWR_ON */
- mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
/* release DA_MP_PLL_ISO_EN */
- mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
/* release DA_MP_CDR_PWR_ON */
- mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
- mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
/* release DA_MP_CDR_ISO_EN */
- mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
- mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
/* release DA_MP_RX0_SQ_EN */
- mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
- mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
/* delay 1us to wait DIFZ stable */
udelay(1);
/* release DIFZ */
- mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
}
static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
{
+ void __iomem *mmio = phy->mmio;
+
/* force DIFZ */
- mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
/* force DA_MP_RX0_SQ_EN */
- mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
- mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
/* force DA_MP_CDR_ISO_EN */
- mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
- mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
/* force DA_MP_CDR_PWR_ON */
- mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
- mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
/* force DA_MP_PLL_ISO_EN */
- mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
- mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
/* force DA_MP_PLL_PWR_ON */
- mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
}
static int ufs_mtk_phy_power_on(struct phy *generic_phy)
--
2.18.0
Powered by blists - more mailing lists