linux-kernel - [PATCH v7 4/5] phy: qcom: Add power suspend & resume callbacks to PCIe phy

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Message-Id: <1663669347-29308-5-git-send-email-quic_krichai@quicinc.com>
Date:   Tue, 20 Sep 2022 15:52:26 +0530
From:   Krishna chaitanya chundru <quic_krichai@...cinc.com>
To:     helgaas@...nel.org
Cc:     linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, mka@...omium.org,
        quic_vbadigan@...cinc.com, quic_hemantk@...cinc.com,
        quic_nitegupt@...cinc.com, quic_skananth@...cinc.com,
        quic_ramkri@...cinc.com, manivannan.sadhasivam@...aro.org,
        swboyd@...omium.org, dmitry.baryshkov@...aro.org,
        svarbanov@...sol.com, agross@...nel.org, andersson@...nel.org,
        konrad.dybcio@...ainline.org, lpieralisi@...nel.org,
        robh@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
        linux-phy@...ts.infradead.org, vkoul@...nel.org, kishon@...com,
        mturquette@...libre.com, linux-clk@...r.kernel.org,
        Krishna chaitanya chundru <quic_krichai@...cinc.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>
Subject: [PATCH v7 4/5] phy: qcom: Add power suspend & resume callbacks to PCIe phy

Add phy power suspend & resume callbacks to PCIe phy. Using these
callbacks we can release phy resources like phy specific clocks
but continue maintain PCIe link in l1ss state.

This can help in parking PCIe link in l1ss state during system
suspend (S3).

Instead of this if we add suspend & resume pm ops, phy will suspend
first instead of PCIe driver, it will cause link down as phy will
be down before controller goes down.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
changes since v6:
	- Change names from phy_power_down and phy_power_up to
	  phy_pm_suspend and phy_pm_resume respectively.
---
 drivers/pci/controller/dwc/pcie-qcom.c   |  4 +--
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 50 ++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7a6f69e..672a9be 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1326,7 +1326,7 @@ static int qcom_pcie_resume_2_7_0(struct qcom_pcie *pcie)
 
 	ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
 
-	phy_power_on(pcie->phy);
+	phy_pm_resume(pcie->phy);
 
 	return ret;
 }
@@ -1335,7 +1335,7 @@ static int qcom_pcie_suspend_2_7_0(struct qcom_pcie *pcie)
 {
 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
 
-	phy_power_off(pcie->phy);
+	phy_pm_suspend(pcie->phy);
 
 	clk_bulk_disable_unprepare(res->num_clks, res->clks);
 	return 0;
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2d65e1f..69220dd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2145,6 +2145,54 @@ static int qcom_qmp_phy_pcie_exit(struct phy *phy)
 	return 0;
 }
 
+static int qcom_qmp_phy_pcie_resume(struct phy *phy)
+{
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
+	struct qcom_qmp *qmp = qphy->qmp;
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(qphy->pipe_clk);
+	if (ret)
+		return ret;
+
+	/* Pull out PHY from POWER DOWN state */
+	if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+		qphy_setbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+			     cfg->pwrdn_ctrl);
+	} else {
+		qphy_setbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
+				cfg->pwrdn_ctrl);
+	}
+
+	return 0;
+}
+
+static int qcom_qmp_phy_pcie_suspend(struct phy *phy)
+{
+	struct qmp_phy *qphy = phy_get_drvdata(phy);
+	struct qcom_qmp *qmp = qphy->qmp;
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
+
+	clk_disable_unprepare(qphy->pipe_clk);
+	clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
+
+	/* Put PHY into POWER DOWN state: active low */
+	if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+		qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+			     cfg->pwrdn_ctrl);
+	} else {
+		qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
+				cfg->pwrdn_ctrl);
+	}
+
+	return 0;
+}
+
 static int qcom_qmp_phy_pcie_enable(struct phy *phy)
 {
 	int ret;
@@ -2304,6 +2352,8 @@ static const struct phy_ops qcom_qmp_phy_pcie_ops = {
 	.power_on	= qcom_qmp_phy_pcie_enable,
 	.power_off	= qcom_qmp_phy_pcie_disable,
 	.set_mode	= qcom_qmp_phy_pcie_set_mode,
+	.suspend	= qcom_qmp_phy_pcie_suspend,
+	.resume		= qcom_qmp_phy_pcie_resume,
 	.owner		= THIS_MODULE,
 };
 
-- 
2.7.4