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Message-Id: <20220815-rpi-fix-4k-60-v2-7-983276b83f62@cerno.tech>
Date: Tue, 20 Sep 2022 14:50:26 +0200
From: Maxime Ripard <maxime@...no.tech>
To: Daniel Vetter <daniel@...ll.ch>,
Florian Fainelli <f.fainelli@...il.com>,
David Airlie <airlied@...ux.ie>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
Michael Turquette <mturquette@...libre.com>,
Scott Branden <sbranden@...adcom.com>,
Stephen Boyd <sboyd@...nel.org>, Emma Anholt <emma@...olt.net>,
Ray Jui <rjui@...adcom.com>, Maxime Ripard <mripard@...nel.org>
Cc: linux-rpi-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Dom Cobley <popcornmix@...il.com>,
dri-devel@...ts.freedesktop.org, Maxime Ripard <maxime@...no.tech>,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v2 7/7] drm/vc4: Make sure we don't end up with a core clock too high
Following the clock rate range improvements to the clock framework,
trying to set a disjoint range on a clock will now result in an error.
Thus, we can't set a minimum rate higher than the maximum reported by
the firmware, or clk_set_min_rate() will fail.
Thus we need to clamp the rate we are about to ask for to the maximum
rate possible on that clock.
Signed-off-by: Maxime Ripard <maxime@...no.tech>
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index b45dcdfd7306..d241620fd5a7 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -397,8 +397,8 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
if (vc4->is_vc5) {
unsigned long state_rate = max(old_hvs_state->core_clock_rate,
new_hvs_state->core_clock_rate);
- unsigned long core_rate = max_t(unsigned long,
- 500000000, state_rate);
+ unsigned long core_rate = clamp_t(unsigned long, state_rate,
+ 500000000, hvs->max_core_rate);
drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
@@ -432,14 +432,17 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
drm_atomic_helper_cleanup_planes(dev, state);
if (vc4->is_vc5) {
- drm_dbg(dev, "Running the core clock at %lu Hz\n",
- new_hvs_state->core_clock_rate);
+ unsigned long core_rate = min_t(unsigned long,
+ hvs->max_core_rate,
+ new_hvs_state->core_clock_rate);
+
+ drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate);
/*
* Request a clock rate based on the current HVS
* requirements.
*/
- WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
+ WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
clk_get_rate(hvs->core_clk));
--
b4 0.10.0
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