lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 20 Sep 2022 15:50:52 +0200
From:   Neil Armstrong <neil.armstrong@...aro.org>
To:     Johan Hovold <johan+linaro@...nel.org>,
        Vinod Koul <vkoul@...nel.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/17] phy: qcom-qmp-pcie: drop unused type from config

On 20/09/2022 09:38, Johan Hovold wrote:
> The configuration PHY type is no longer used since the QMP driver split
> so drop it from the configurations.
> 
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> ---
>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 --------------
>   1 file changed, 14 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 4939edcd8cb1..d25f9215b86f 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -1304,8 +1304,6 @@ struct qmp_phy;
>   
>   /* struct qmp_phy_cfg - per-PHY initialization config */
>   struct qmp_phy_cfg {
> -	/* phy-type - PCIE/UFS/USB */
> -	unsigned int type;
>   	/* number of lanes provided by phy */
>   	int nlanes;
>   
> @@ -1470,7 +1468,6 @@ static const char * const sdm845_pciephy_reset_l[] = {
>   };
>   
>   static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> -	.type			= PHY_TYPE_PCIE,
>   	.nlanes			= 1,
>   
>   	.serdes_tbl		= ipq8074_pcie_serdes_tbl,
> @@ -1499,7 +1496,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
> -	.type			= PHY_TYPE_PCIE,
>   	.nlanes			= 1,
>   
>   	.serdes_tbl		= ipq8074_pcie_gen3_serdes_tbl,
> @@ -1529,7 +1525,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
> -	.type			= PHY_TYPE_PCIE,
>   	.nlanes			= 1,
>   
>   	.serdes_tbl		= ipq6018_pcie_serdes_tbl,
> @@ -1559,7 +1554,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 1,
>   
>   	.serdes_tbl		= sdm845_qmp_pcie_serdes_tbl,
> @@ -1590,7 +1584,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 1,
>   
>   	.serdes_tbl		= sdm845_qhp_pcie_serdes_tbl,
> @@ -1619,7 +1612,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 1,
>   
>   	.serdes_tbl		= sm8250_qmp_pcie_serdes_tbl,
> @@ -1658,7 +1650,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 2,
>   
>   	.serdes_tbl		= sm8250_qmp_pcie_serdes_tbl,
> @@ -1698,7 +1689,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
> -	.type			= PHY_TYPE_PCIE,
>   	.nlanes			= 1,
>   
>   	.serdes_tbl		= msm8998_pcie_serdes_tbl,
> @@ -1723,7 +1713,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 1,
>   
>   	.serdes_tbl		= sc8180x_qmp_pcie_serdes_tbl,
> @@ -1753,7 +1742,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 2,
>   
>   	.serdes_tbl		= sdx55_qmp_pcie_serdes_tbl,
> @@ -1785,7 +1773,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 1,
>   
>   	.serdes_tbl		= sm8450_qmp_gen3x1_pcie_serdes_tbl,
> @@ -1816,7 +1803,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
>   };
>   
>   static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> -	.type = PHY_TYPE_PCIE,
>   	.nlanes = 2,
>   
>   	.serdes_tbl		= sm8450_qmp_gen4x2_pcie_serdes_tbl,

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ