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Message-Id: <20220921214439.1491510-6-stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 14:43:48 -0700
From: Chris Stillson <stillson@...osinc.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Guo Ren <guoren@...ux.alibaba.com>,
Vincent Chen <vincent.chen@...ive.com>,
Han-Kuan Chen <hankuan.chen@...ive.com>,
Greentime Hu <greentime.hu@...ive.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <keescook@...omium.org>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Oleg Nesterov <oleg@...hat.com>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Guo Ren <guoren@...nel.org>,
Chris Stillson <stillson@...osinc.com>,
Mayuresh Chitale <mchitale@...tanamicro.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Alexandre Ghiti <alexandre.ghiti@...onical.com>,
Qinglin Pan <panqinglin2020@...as.ac.cn>,
Arnd Bergmann <arnd@...db.de>,
Heiko Stuebner <heiko@...ech.de>,
Jisheng Zhang <jszhang@...nel.org>,
Dao Lu <daolu@...osinc.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Sunil V L <sunilvl@...tanamicro.com>,
Ruinland Tsai <ruinland.tsai@...ive.com>,
Li Zhengyu <lizhengyu3@...wei.com>,
Alexander Graf <graf@...zon.com>,
Ard Biesheuvel <ardb@...nel.org>,
Tsukasa OI <research_trasio@....a4lg.com>,
Yury Norov <yury.norov@...il.com>,
Nicolas Saenz Julienne <nsaenzju@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Frederic Weisbecker <frederic@...nel.org>,
Changbin Du <changbin.du@...el.com>,
Vitaly Wool <vitaly.wool@...sulko.com>,
Myrtle Shah <gatecat@....me>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>,
Alexey Dobriyan <adobriyan@...il.com>,
Huacai Chen <chenhuacai@...nel.org>,
Janosch Frank <frankja@...ux.ibm.com>,
Christian Brauner <brauner@...nel.org>,
Peter Collingbourne <pcc@...gle.com>,
Eugene Syromiatnikov <esyr@...hat.com>,
Colin Cross <ccross@...gle.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Barret Rhoden <brho@...gle.com>,
Suren Baghdasaryan <surenb@...gle.com>,
Davidlohr Bueso <dave@...olabs.net>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mm@...ck.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org
Subject: [PATCH v12 06/17] riscv: Reset vector register
From: Guo Ren <guoren@...ux.alibaba.com>
Reset vector registers at boot-time and disable vector instructions
execution for kernel mode.
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@...ive.com>
Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
Co-developed-by: Han-Kuan Chen <hankuan.chen@...ive.com>
Signed-off-by: Han-Kuan Chen <hankuan.chen@...ive.com>
Co-developed-by: Greentime Hu <greentime.hu@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Reviewed-by: Palmer Dabbelt <palmer@...osinc.com>
---
arch/riscv/kernel/entry.S | 6 +++---
arch/riscv/kernel/head.S | 35 +++++++++++++++++++++++++++++------
2 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index b9eda3fcbd6d..1e9987376591 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -77,10 +77,10 @@ _save_context:
* Disable user-mode memory access as it should only be set in the
* actual user copy routines.
*
- * Disable the FPU to detect illegal usage of floating point in kernel
- * space.
+ * Disable the FPU/Vector to detect illegal usage of floating point
+ * or vector in kernel space.
*/
- li t0, SR_SUM | SR_FS
+ li t0, SR_SUM | SR_FS | SR_VS
REG_L s0, TASK_TI_USER_SP(tp)
csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index b865046e4dbb..2c81ca42ec4e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -140,10 +140,10 @@ secondary_start_sbi:
.option pop
/*
- * Disable FPU to detect illegal usage of
- * floating point in kernel space
+ * Disable FPU & VECTOR to detect illegal usage of
+ * floating point or vector in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS | SR_VS
csrc CSR_STATUS, t0
/* Set trap vector to spin forever to help debug */
@@ -234,10 +234,10 @@ pmp_done:
.option pop
/*
- * Disable FPU to detect illegal usage of
- * floating point in kernel space
+ * Disable FPU & VECTOR to detect illegal usage of
+ * floating point or vector in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS | SR_VS
csrc CSR_STATUS, t0
#ifdef CONFIG_RISCV_BOOT_SPINWAIT
@@ -431,6 +431,29 @@ ENTRY(reset_regs)
csrw fcsr, 0
/* note that the caller must clear SR_FS */
#endif /* CONFIG_FPU */
+
+#ifdef CONFIG_VECTOR
+ csrr t0, CSR_MISA
+ li t1, COMPAT_HWCAP_ISA_V
+ and t0, t0, t1
+ beqz t0, .Lreset_regs_done
+
+ /*
+ * Clear vector registers and reset vcsr
+ * VLMAX has a defined value, VLEN is a constant,
+ * and this form of vsetvli is defined to set vl to VLMAX.
+ */
+ li t1, SR_VS
+ csrs CSR_STATUS, t1
+ csrs CSR_VCSR, x0
+ vsetvli t1, x0, e8, m8, ta, ma
+ vmv.v.i v0, 0
+ vmv.v.i v8, 0
+ vmv.v.i v16, 0
+ vmv.v.i v24, 0
+ /* note that the caller must clear SR_VS */
+#endif /* CONFIG_VECTOR */
+
.Lreset_regs_done:
ret
END(reset_regs)
--
2.25.1
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