| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20220921214439.1491510-11-stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 14:43:53 -0700
From: Chris Stillson <stillson@...osinc.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Vincent Chen <vincent.chen@...ive.com>,
Greentime Hu <greentime.hu@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <keescook@...omium.org>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Oleg Nesterov <oleg@...hat.com>, Guo Ren <guoren@...nel.org>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Chris Stillson <stillson@...osinc.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Qinglin Pan <panqinglin2020@...as.ac.cn>,
Alexandre Ghiti <alexandre.ghiti@...onical.com>,
Arnd Bergmann <arnd@...db.de>,
Heiko Stuebner <heiko@...ech.de>, Dao Lu <daolu@...osinc.com>,
Jisheng Zhang <jszhang@...nel.org>,
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Sunil V L <sunilvl@...tanamicro.com>,
Ruinland Tsai <ruinland.tsai@...ive.com>,
Han-Kuan Chen <hankuan.chen@...ive.com>,
Li Zhengyu <lizhengyu3@...wei.com>,
Alexander Graf <graf@...zon.com>,
Ard Biesheuvel <ardb@...nel.org>,
Tsukasa OI <research_trasio@....a4lg.com>,
Yury Norov <yury.norov@...il.com>,
"Paul E. McKenney" <paulmck@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Frederic Weisbecker <frederic@...nel.org>,
Changbin Du <changbin.du@...el.com>,
Myrtle Shah <gatecat@....me>,
Vitaly Wool <vitaly.wool@...sulko.com>,
Catalin Marinas <catalin.marinas@....com>,
Mark Brown <broonie@...nel.org>, Will Deacon <will@...nel.org>,
Janosch Frank <frankja@...ux.ibm.com>,
Alexey Dobriyan <adobriyan@...il.com>,
Huacai Chen <chenhuacai@...nel.org>,
Christian Brauner <brauner@...nel.org>,
Evgenii Stepanov <eugenis@...gle.com>,
Peter Collingbourne <pcc@...gle.com>,
Eugene Syromiatnikov <esyr@...hat.com>,
Colin Cross <ccross@...gle.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Suren Baghdasaryan <surenb@...gle.com>,
Barret Rhoden <brho@...gle.com>,
Davidlohr Bueso <dave@...olabs.net>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mm@...ck.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org
Subject: [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv
From: Vincent Chen <vincent.chen@...ive.com>
The vector register belongs to the signal context. They need to be stored
and restored as entering and leaving the signal handler. According to the
V-extension specification, the maximum length of the vector registers can
be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a
sigframe, it may not be enough. To resolve this problem, this patch refers
to the commit 94b07c1f8c39c
("arm64: signal: Report signal frame size to userspace via auxv") to enable
userspace to know the minimum required sigframe size through the auxiliary
vector and use it to allocate enough memory for signal context.
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
---
arch/riscv/include/asm/elf.h | 47 +++++++++++++++-------------
arch/riscv/include/asm/processor.h | 2 ++
arch/riscv/include/uapi/asm/auxvec.h | 1 +
arch/riscv/kernel/signal.c | 8 +++++
4 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index 14fc7342490b..df9047b619e8 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -77,28 +77,31 @@ extern unsigned long elf_hwcap;
#define COMPAT_ELF_PLATFORM (NULL)
#ifdef CONFIG_MMU
-#define ARCH_DLINFO \
-do { \
- /* \
- * Note that we add ulong after elf_addr_t because \
- * casting current->mm->context.vdso triggers a cast \
- * warning of cast from pointer to integer for \
- * COMPAT ELFCLASS32. \
- */ \
- NEW_AUX_ENT(AT_SYSINFO_EHDR, \
- (elf_addr_t)(ulong)current->mm->context.vdso); \
- NEW_AUX_ENT(AT_L1I_CACHESIZE, \
- get_cache_size(1, CACHE_TYPE_INST)); \
- NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \
- get_cache_geometry(1, CACHE_TYPE_INST)); \
- NEW_AUX_ENT(AT_L1D_CACHESIZE, \
- get_cache_size(1, CACHE_TYPE_DATA)); \
- NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \
- get_cache_geometry(1, CACHE_TYPE_DATA)); \
- NEW_AUX_ENT(AT_L2_CACHESIZE, \
- get_cache_size(2, CACHE_TYPE_UNIFIED)); \
- NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \
- get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \
+#define ARCH_DLINFO \
+do { \
+ NEW_AUX_ENT(AT_SYSINFO_EHDR, \
+ (elf_addr_t)current->mm->context.vdso); \
+ NEW_AUX_ENT(AT_L1I_CACHESIZE, \
+ get_cache_size(1, CACHE_TYPE_INST)); \
+ NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \
+ get_cache_geometry(1, CACHE_TYPE_INST)); \
+ NEW_AUX_ENT(AT_L1D_CACHESIZE, \
+ get_cache_size(1, CACHE_TYPE_DATA)); \
+ NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \
+ get_cache_geometry(1, CACHE_TYPE_DATA)); \
+ NEW_AUX_ENT(AT_L2_CACHESIZE, \
+ get_cache_size(2, CACHE_TYPE_UNIFIED)); \
+ NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \
+ get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \
+ /* \
+ * Should always be nonzero unless there's a kernel bug. \
+ * If we haven't determined a sensible value to give to \
+ * userspace, omit the entry: \
+ */ \
+ if (likely(signal_minsigstksz)) \
+ NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \
+ else \
+ NEW_AUX_ENT(AT_IGNORE, 0); \
} while (0)
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
struct linux_binprm;
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 95917a2b24f9..a09141ecf6aa 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -7,6 +7,7 @@
#define _ASM_RISCV_PROCESSOR_H
#include <linux/const.h>
+#include <linux/cache.h>
#include <vdso/processor.h>
@@ -86,6 +87,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
extern void riscv_fill_hwcap(void);
extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+extern unsigned long signal_minsigstksz __ro_after_init;
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
index 32c73ba1d531..6610d24e6662 100644
--- a/arch/riscv/include/uapi/asm/auxvec.h
+++ b/arch/riscv/include/uapi/asm/auxvec.h
@@ -33,5 +33,6 @@
/* entries in ARCH_DLINFO */
#define AT_VECTOR_SIZE_ARCH 7
+#define AT_MINSIGSTKSZ 51
#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index 41d9a02c7098..fb1f5012416e 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -478,8 +478,16 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs,
resume_user_mode_work(regs);
}
+unsigned long __ro_after_init signal_minsigstksz;
+
void init_rt_signal_env(void);
void __init init_rt_signal_env(void)
{
rvv_sc_size = sizeof(struct __sc_riscv_v_state) + riscv_vsize;
+ /*
+ * Determine the stack space required for guaranteed signal delivery.
+ * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry
+ * in the auxiliary array at process startup.
+ */
+ signal_minsigstksz = cal_rt_frame_size();
}
--
2.25.1
Powered by blists - more mailing lists