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Message-Id: <20220921214439.1491510-15-stillson@rivosinc.com>
Date:   Wed, 21 Sep 2022 14:43:57 -0700
From:   Chris Stillson <stillson@...osinc.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     Vincent Chen <vincent.chen@...ive.com>,
        Greentime Hu <greentime.hu@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Eric Biederman <ebiederm@...ssion.com>,
        Kees Cook <keescook@...omium.org>,
        Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...shpatra.org>,
        Oleg Nesterov <oleg@...hat.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Guo Ren <guoren@...nel.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
        Chris Stillson <stillson@...osinc.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Qinglin Pan <panqinglin2020@...as.ac.cn>,
        Alexandre Ghiti <alexandre.ghiti@...onical.com>,
        Arnd Bergmann <arnd@...db.de>,
        Heiko Stuebner <heiko@...ech.de>,
        Jisheng Zhang <jszhang@...nel.org>,
        Dao Lu <daolu@...osinc.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Nick Knight <nick.knight@...ive.com>,
        Han-Kuan Chen <hankuan.chen@...ive.com>,
        Changbin Du <changbin.du@...el.com>,
        Li Zhengyu <lizhengyu3@...wei.com>,
        Ard Biesheuvel <ardb@...nel.org>,
        Tsukasa OI <research_trasio@....a4lg.com>,
        Yury Norov <yury.norov@...il.com>,
        Frederic Weisbecker <frederic@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Vitaly Wool <vitaly.wool@...sulko.com>,
        Myrtle Shah <gatecat@....me>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>,
        Janosch Frank <frankja@...ux.ibm.com>,
        Huacai Chen <chenhuacai@...nel.org>,
        Alexey Dobriyan <adobriyan@...il.com>,
        Christian Brauner <brauner@...nel.org>,
        Vincenzo Frascino <Vincenzo.Frascino@....com>,
        Eugene Syromiatnikov <esyr@...hat.com>,
        Colin Cross <ccross@...gle.com>,
        Peter Collingbourne <pcc@...gle.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Barret Rhoden <brho@...gle.com>,
        Suren Baghdasaryan <surenb@...gle.com>,
        Davidlohr Bueso <dave@...olabs.net>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mm@...ck.org, kvm@...r.kernel.org,
        kvm-riscv@...ts.infradead.org
Subject: [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list

From: Vincent Chen <vincent.chen@...ive.com>

Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU
to support V extension.

Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 6f59ec64175e..b242ed155262 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -35,6 +35,7 @@ extern unsigned long elf_hwcap;
 #define RISCV_ISA_EXT_m		('m' - 'a')
 #define RISCV_ISA_EXT_s		('s' - 'a')
 #define RISCV_ISA_EXT_u		('u' - 'a')
+#define RISCV_ISA_EXT_v		('v' - 'a')
 
 /*
  * Increse this to higher value as kernel support more ISA extensions.
-- 
2.25.1

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