lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <OS0PR01MB59220E0803C83EC63954340E864F9@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Date:   Wed, 21 Sep 2022 05:22:23 +0000
From:   Biju Das <biju.das.jz@...renesas.com>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
CC:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Heiko Stuebner <heiko@...ech.de>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Atish Patra <atishp@...osinc.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes

Hi Prabhakar,

> Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
> 
> Hi Biju,
> 
> On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@...renesas.com>
> wrote:
> >
> >
> > Just ignore my mail, As I realised IRQ property in each node will be
> a problem.
> >
> Yes the IRQ numbers are different (offset of 32) along with the IRQ
> parent.
> 
> Refer this thread [0] where other SoC vendors have similar issues,
> maybe in future when DTC becomes more clever we can use single SoC
> DTSI for both.

Not sure, May be the macro suggestion mentioned in that thread will work for us??
As it is just only the interrupt properties that differ which is
handled in macro. A Generic macro in common dtsi which is
expanded in RISCV or arm64 specific dtsi to get proper one??

Cheers,
Biju

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ