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Date: Thu, 22 Sep 2022 14:44:09 +0800
From: Xing Zhengjun <zhengjun.xing@...ux.intel.com>
To: Ian Rogers <irogers@...gle.com>
Cc: acme@...nel.org, peterz@...radead.org, mingo@...hat.com,
alexander.shishkin@...el.com, jolsa@...nel.org,
namhyung@...nel.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, ak@...ux.intel.com,
kan.liang@...ux.intel.com
Subject: Re: [PATCH 1/2] perf print-events: Fix "perf list" can not display
the PMU prefix for some hybrid cache events
On 9/22/2022 11:12 AM, Ian Rogers wrote:
> On Wed, Sep 21, 2022 at 6:47 PM <zhengjun.xing@...ux.intel.com> wrote:
>>
>> From: Zhengjun Xing <zhengjun.xing@...ux.intel.com>
>>
>> Some hybrid hardware cache events are only available on one CPU PMU. For
>> example, 'L1-dcache-load-misses' is only available on cpu_core. We have
>> supported in the perf list clearly reporting this info, the function works
>> fine before but recently the argument "config" in API is_event_supported()
>> is changed from "u64" to "unsigned int" which caused a regression, the
>> "perf list" then can not display the PMU prefix for some hybrid cache
>> events. For the hybrid systems, the PMU type ID is stored at config[63:32],
>> define config to "unsigned int" will miss the PMU type ID information, then
>> the regression happened, the config should be defined as "u64".
>>
>> Before:
>> # ./perf list |grep "Hardware cache event"
>> L1-dcache-load-misses [Hardware cache event]
>> L1-dcache-loads [Hardware cache event]
>> L1-dcache-stores [Hardware cache event]
>> L1-icache-load-misses [Hardware cache event]
>> L1-icache-loads [Hardware cache event]
>> LLC-load-misses [Hardware cache event]
>> LLC-loads [Hardware cache event]
>> LLC-store-misses [Hardware cache event]
>> LLC-stores [Hardware cache event]
>> branch-load-misses [Hardware cache event]
>> branch-loads [Hardware cache event]
>> dTLB-load-misses [Hardware cache event]
>> dTLB-loads [Hardware cache event]
>> dTLB-store-misses [Hardware cache event]
>> dTLB-stores [Hardware cache event]
>> iTLB-load-misses [Hardware cache event]
>> node-load-misses [Hardware cache event]
>> node-loads [Hardware cache event]
>>
>> After:
>> # ./perf list |grep "Hardware cache event"
>> L1-dcache-loads [Hardware cache event]
>> L1-dcache-stores [Hardware cache event]
>> L1-icache-load-misses [Hardware cache event]
>> LLC-load-misses [Hardware cache event]
>> LLC-loads [Hardware cache event]
>> LLC-store-misses [Hardware cache event]
>> LLC-stores [Hardware cache event]
>> branch-load-misses [Hardware cache event]
>> branch-loads [Hardware cache event]
>> cpu_atom/L1-icache-loads/ [Hardware cache event]
>> cpu_core/L1-dcache-load-misses/ [Hardware cache event]
>> cpu_core/node-load-misses/ [Hardware cache event]
>> cpu_core/node-loads/ [Hardware cache event]
>> dTLB-load-misses [Hardware cache event]
>> dTLB-loads [Hardware cache event]
>> dTLB-store-misses [Hardware cache event]
>> dTLB-stores [Hardware cache event]
>> iTLB-load-misses [Hardware cache event]
>>
>> Fixes: 9b7c7728f4e4 ("perf parse-events: Break out tracepoint and printing")
>> Signed-off-by: Zhengjun Xing <zhengjun.xing@...ux.intel.com>
>> Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
>
> Acked-by: Ian Rogers <irogers@...gle.com>
>
> Sorry for this breakage, I suspect that a long review on the
> refactoring CL meant that I missed the intervening fix. Can we add a
> test on this? It would need to be hybrid specific and skip otherwise.
Thanks. I will add a test case for hybrid-specific later.
>
> Thanks,
> Ian
>
>> ---
>> tools/perf/util/print-events.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c
>> index ba1ab5134685..04050d4f6db8 100644
>> --- a/tools/perf/util/print-events.c
>> +++ b/tools/perf/util/print-events.c
>> @@ -239,7 +239,7 @@ void print_sdt_events(const char *subsys_glob, const char *event_glob,
>> strlist__delete(sdtlist);
>> }
>>
>> -static bool is_event_supported(u8 type, unsigned int config)
>> +static bool is_event_supported(u8 type, u64 config)
>> {
>> bool ret = true;
>> int open_return;
>> --
>> 2.25.1
>>
--
Zhengjun Xing
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