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Message-ID: <966b46f5-ed3b-9daa-4cfb-602a534a8bfc@linaro.org>
Date: Fri, 23 Sep 2022 19:49:22 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Dinh Nguyen <dinguyen@...nel.org>, jh80.chung@...sung.com
Cc: ulf.hansson@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-mmc@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCHv2 1/3] dt-bindings: mmc: synopsys-dw-mshc: document
"altr,sysmgr-syscon"
On 23/09/2022 00:03, Dinh Nguyen wrote:
> Document the optional "altr,sysmgr-syscon" binding that is used to
> access the System Manager register that controls the SDMMC clock
> phase.
>
> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
Thank you for your patch. There is something to discuss/improve.
> ---
> v2: added
> ---
> .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> index ae6d6fca79e2..aece6a337262 100644
> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> @@ -38,6 +38,18 @@ properties:
> - const: biu
> - const: ciu
>
> + altr,sysmgr-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to the sysmgr node
> + - description: register offset that controls the SDMMC clock phase
> + description:
> + Contains the phandle to System Manager block that contains
> + the SDMMC clock-phase control register. The first value is the pointer
> + to the sysmgr and the 2nd value is the register offset for the SDMMC
> + clock phase register.
You need to restrict it per variant (altera). Move the allOf from top of
the file to place above unevaluatedProperties and add if:then: making it
false for other variants.
Best regards,
Krzysztof
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