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Message-ID: <CAPOBaE42Rzq63d11i=9Ck1rjb3hdxOe81NWPc1QVQ7P0MWu1Vw@mail.gmail.com>
Date: Fri, 23 Sep 2022 13:57:34 -0700
From: Han Jingoo <jingoohan1@...il.com>
To: Vidya Sagar <vidyas@...dia.com>
Cc: gustavo.pimentel@...opsys.com, lpieralisi@...nel.org,
robh@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
kthota@...dia.com, mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V1] PCI: dwc: Fixes N_FTS setup
On Mon, Sep 19, 2022, Vidya Sagar <vidyas@...dia.com> wrote:
>
> commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup")
> unnecessarily uses pci->link_gen in deriving the index to the
> n_fts[] array also introducing the issue of accessing beyond the
> boundaries of array for greater than Gen-2 speeds. This change fixes
> that issue.
>
> Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup")
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
Acked-by: Jingoo Han <jingoohan1@...il.com>
Please send a V2 patch that addresses Bjorn's feedback.
Thank you.
Best regards,
Jingoo Han
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index c6725c519a47..9e4d96e5a3f5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -641,7 +641,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> if (pci->n_fts[1]) {
> val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> val &= ~PORT_LOGIC_N_FTS_MASK;
> - val |= pci->n_fts[pci->link_gen - 1];
> + val |= pci->n_fts[1];
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> }
>
> --
> 2.17.1
>
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