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Message-ID: <77bbe256-f684-04c2-b78f-58bcc89f4755@nvidia.com>
Date: Fri, 23 Sep 2022 11:06:56 +0100
From: Jon Hunter <jonathanh@...dia.com>
To: Akhil R <akhilrajeev@...dia.com>, ldewangan@...dia.com,
vkoul@...nel.org, thierry.reding@...il.com, p.zabel@...gutronix.de,
dmaengine@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/3] arm64: tegra: Add dma-channel-mask in GPCDMA node
On 19/09/2022 12:25, Akhil R wrote:
> Add dma-channel-mask property in Tegra GPCDMA device tree node.
>
> The property would help to specify the channels to be used in
> kernel and reserve few for the firmware. This was previously
> achieved by limiting the channel number to 31 in the driver.
> Now since we can list all 32 channels, update the interrupts
> property as well to list all 32 interrupts.
>
> Signed-off-by: Akhil R <akhilrajeev@...dia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++-
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++-
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++-
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 3580fbf99091..13a84e34e094 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -78,7 +78,8 @@
> reg = <0x0 0x2600000 0x0 0x210000>;
> resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -112,6 +113,7 @@
> #dma-cells = <1>;
> iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> dma-coherent;
> + dma-channel-mask = <0xfffffffe>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 9176c4b27133..593fbf22b34f 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -142,7 +142,8 @@
> reg = <0x2600000 0x210000>;
> resets = <&bpmp TEGRA194_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -176,6 +177,7 @@
> #dma-cells = <1>;
> iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
> dma-coherent;
> + dma-channel-mask = <0xfffffffe>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 5852e765ad90..afd90b72cdea 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -28,7 +28,8 @@
> reg = <0x2600000 0x210000>;
> resets = <&bpmp TEGRA234_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -61,6 +62,7 @@
> <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> #dma-cells = <1>;
> iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
> + dma-channel-mask = <0xfffffffe>;
> dma-coherent;
> };
>
Reviewed-by: Jon Hunter <jonathanh@...dia.com>
Thanks!
Jon
--
nvpublic
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