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Message-ID: <Yy2jbsaXuoxgR+fj@nvidia.com>
Date:   Fri, 23 Sep 2022 09:15:42 -0300
From:   Jason Gunthorpe <jgg@...dia.com>
To:     Baolu Lu <baolu.lu@...ux.intel.com>
Cc:     Joerg Roedel <joro@...tes.org>,
        Christoph Hellwig <hch@...radead.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Kevin Tian <kevin.tian@...el.com>,
        Ashok Raj <ashok.raj@...el.com>, Will Deacon <will@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
        Jean-Philippe Brucker <jean-philippe@...aro.com>,
        Dave Jiang <dave.jiang@...el.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Vinod Koul <vkoul@...nel.org>,
        Eric Auger <eric.auger@...hat.com>,
        Liu Yi L <yi.l.liu@...el.com>,
        Jacob jun Pan <jacob.jun.pan@...el.com>,
        Zhangfei Gao <zhangfei.gao@...aro.org>,
        Zhu Tony <tony.zhu@...el.com>, iommu@...ts.linux.dev,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v13 07/13] iommu/vt-d: Add SVA domain support

On Fri, Sep 23, 2022 at 10:21:51AM +0800, Baolu Lu wrote:

> At the beginning of this project, I wanted to consolidate the mm
> notifications into the core. However, ARM SMMUv3 and Intel handle the mm
> notifications a little differently. Then I decided to do this work
> separately from the current series.

It doesn't look really different..

The SVA iommu domain needs two new ops triggered by the notifier:

 - 'stop using the mm, subsitute a blocking domain' tied to release
 - Cache invalidate a range, maybe this is just iotlb_sync_map()

And we could even think about the first as the core code literally
attaching a dummy blocking domain and releasing the SVA domain. There
is no reason we need to have every driver do this tricky bit of
lifecycle management.

Jason

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