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Message-ID: <CAM2SziUBmXcte+GGsXPyKC7ce5EVjaiiWGAU=bWev2LAWrHYrA@mail.gmail.com>
Date:   Fri, 23 Sep 2022 09:27:01 -0700
From:   Chris Stillson <stillson@...osinc.com>
To:     Samuel Holland <samuel@...lland.org>
Cc:     Greentime Hu <greentime.hu@...ive.com>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Vincent Chen <vincent.chen@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Eric Biederman <ebiederm@...ssion.com>,
        Kees Cook <keescook@...omium.org>,
        Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...shpatra.org>,
        Oleg Nesterov <oleg@...hat.com>, Guo Ren <guoren@...nel.org>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Alexandre Ghiti <alexandre.ghiti@...onical.com>,
        Arnd Bergmann <arnd@...db.de>,
        Heiko Stuebner <heiko@...ech.de>,
        Jisheng Zhang <jszhang@...nel.org>,
        Dao Lu <daolu@...osinc.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Ruinland Tsai <ruinland.tsai@...ive.com>,
        Han-Kuan Chen <hankuan.chen@...ive.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save
 vector features.

(resending, as I forgot to set it to plain mail)

This is the way the original set of patches worked. I tried to change
them as little as possible for the rebase.

On Wed, Sep 21, 2022 at 9:23 PM Samuel Holland <samuel@...lland.org> wrote:
>
> On 9/21/22 16:43, Chris Stillson wrote:
> > From: Greentime Hu <greentime.hu@...ive.com>
> >
> > This patch is used to detect vector support status of CPU and use
> > riscv_vsize to save the size of all the vector registers. It assumes
> > all harts has the same capabilities in SMP system.
> >
> > [guoren@...ux.alibaba.com: add has_vector checking]
> > Co-developed-by: Guo Ren <guoren@...ux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> > Co-developed-by: Vincent Chen <vincent.chen@...ive.com>
> > Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> > ---
> >  arch/riscv/include/asm/vector.h | 14 +++++
> >  arch/riscv/kernel/cpufeature.c  | 19 +++++++
> >  arch/riscv/kernel/riscv_ksyms.c |  6 +++
> >  arch/riscv/kernel/vector.S      | 93 +++++++++++++++++++++++++++++++++
>
> This file is not added to the Makefile until patch 8.
>
> >  4 files changed, 132 insertions(+)
> >  create mode 100644 arch/riscv/include/asm/vector.h
> >  create mode 100644 arch/riscv/kernel/vector.S
>

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