linux-kernel - Re: [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1

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Message-ID: <Yy6/6nPa8buvqvbp@debian.me>
Date:   Sat, 24 Sep 2022 15:29:30 +0700
From:   Bagas Sanjaya <bagasdotme@...il.com>
To:     matthew.gerlach@...ux.intel.com
Cc:     hao.wu@...el.com, yilun.xu@...el.com, russell.h.weight@...el.com,
        basheer.ahmed.muddebihal@...el.com, trix@...hat.com,
        mdf@...nel.org, linux-fpga@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
        tianfei.zhang@...el.com, corbet@....net,
        gregkh@...uxfoundation.org, linux-serial@...r.kernel.org,
        jirislaby@...nel.org, geert+renesas@...der.be,
        andriy.shevchenko@...ux.intel.com,
        niklas.soderlund+renesas@...natech.se, phil.edworthy@...esas.com,
        macro@...am.me.uk, johan@...nel.org, lukas@...ner.de
Subject: Re: [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for
 DFHv1

On Fri, Sep 23, 2022 at 05:17:40AM -0700, matthew.gerlach@...ux.intel.com wrote:
> +With DFHv0, the register map of a given feature is located immediately following
> +the DFHv0 in the memory space.  With DFHv1, the location of the feature register
> +map can be specified as an offset to the DFHv1 or as an absolute address.  The DFHv1
> +structure is shown below:
> +
> +    +-----------------------------------------------------------------------+
> +    |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0|
> +    +-----------------------------------------------------------------------+
> +    |63                                 GUID_L                             0|
> +    +-----------------------------------------------------------------------+
> +    |63                                 GUID_H                             0|
> +    +-----------------------------------------------------------------------+
> +    |63                 Address/Offset                            1|  Rel  0|
> +    +-----------------------------------------------------------------------+
> +    |63 Size of register set  32|Params 31|30 Group    16|15 Instance      0|
> +    +-----------------------------------------------------------------------+
> +    |63 Next parameter offset 32|31 Param Version 16|15 Param ID           0|
> +    +-----------------------------------------------------------------------+
> +    |63                 Parameter Data                                     0|
> +    +-----------------------------------------------------------------------+
> +
> +                                  ...
> +
> +    +-----------------------------------------------------------------------+
> +    |63 Next parameter offset 32|31 Param Version 16|15 Param ID           0|
> +    +-----------------------------------------------------------------------+
> +    |63                 Parameter Data                                     0|
> +    +-----------------------------------------------------------------------+
> +

For consistency with DFL location diagram (which is above the DFHv1
diagram above), use literal code block instead of table:

---- >8 ----

diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 7c786b75b4988f..db6bff4aee25eb 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -584,7 +584,7 @@ across all types.
 With DFHv0, the register map of a given feature is located immediately following
 the DFHv0 in the memory space.  With DFHv1, the location of the feature register
 map can be specified as an offset to the DFHv1 or as an absolute address.  The DFHv1
-structure is shown below:
+structure is shown below::
 
     +-----------------------------------------------------------------------+
     |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0|

Thanks.

-- 
An old man doll... just what I always wanted! - Clara

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