linux-kernel - [PATCH 5.19 100/207] ARM: dts: lan966x: Fix the interrupt number for internal PHYs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220926100811.060351218@linuxfoundation.org>
Date:   Mon, 26 Sep 2022 12:11:29 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Horatiu Vultur <horatiu.vultur@...rochip.com>,
        Claudiu Beznea <claudiu.beznea@...rochip.com>,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.19 100/207] ARM: dts: lan966x: Fix the interrupt number for internal PHYs

From: Horatiu Vultur <horatiu.vultur@...rochip.com>

[ Upstream commit f5fc22cbbdcd349402faaddf1a07eb8403658ae8 ]

According to the datasheet the interrupts for internal PHYs are
80 and 81.

Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes")
Signed-off-by: Horatiu Vultur <horatiu.vultur@...rochip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
Link: https://lore.kernel.org/r/20220912192629.461452-1-horatiu.vultur@microchip.com
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/arm/boot/dts/lan966x.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 38e90a31d2dd..25c19f9d0a12 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -515,13 +515,13 @@ mdio1: mdio@...0413c {
 
 			phy0: ethernet-phy@1 {
 				reg = <1>;
-				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			phy1: ethernet-phy@2 {
 				reg = <2>;
-				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 		};
-- 
2.35.1