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Message-ID: <20220926115038.24727-6-vidyas@nvidia.com>
Date: Mon, 26 Sep 2022 17:20:34 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
<bhelgaas@...gle.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <kishon@...com>, <vkoul@...nel.org>,
<mani@...nel.org>, <Sergey.Semin@...kalelectronics.ru>,
<ffclaire1224@...il.com>
CC: <linux-pci@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
<sagar.tv@...il.com>
Subject: [PATCH V2 5/9] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP
PERST# and CLKREQ# pinctrl settings should be applied for both root port
and endpoint mode. Move pinctrl_pm_select_default_state() function call
from root port specific configuration function to probe().
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 0268eacdae48..4ba2a17d92d2 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1659,12 +1659,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
goto fail_pm_get_sync;
}
- ret = pinctrl_pm_select_default_state(dev);
- if (ret < 0) {
- dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
- goto fail_pm_get_sync;
- }
-
ret = tegra_pcie_init_controller(pcie);
if (ret < 0) {
dev_err(dev, "Failed to initialize controller: %d\n", ret);
@@ -2120,6 +2114,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pp = &pci->pp;
pp->num_vectors = MAX_MSI_IRQS;
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret < 0) {
+ const char *level = KERN_ERR;
+
+ if (ret == -EPROBE_DEFER)
+ level = KERN_DEBUG;
+
+ dev_printk(level, dev,
+ "Failed to configure sideband pins: %d\n",
+ ret);
+ return ret;
+ }
+
ret = tegra_pcie_dw_parse_dt(pcie);
if (ret < 0) {
const char *level = KERN_ERR;
--
2.17.1
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