lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220926142938.89608-1-likexu@tencent.com>
Date:   Mon, 26 Sep 2022 22:29:35 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Sean Christopherson <seanjc@...gle.com>,
        Peter Zijlstra <peterz@...radead.org>
Cc:     Kan Liang <kan.liang@...ux.intel.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Jim Mattson <jmattson@...gle.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        x86@...nel.org, kvm@...r.kernel.org
Subject: [PATCH RFC 0/3] KVM: x86/pmu: Add Intel Guest Branch Trace Store Support

When we have support for guest pebs, debug store support is implicitly
supported (if there are no hardware surprises). The debug store based
guest bts feature will also come sooner or later, in a very small effort.

One of reasons for adding the RFC tag is that there are currently two paths
for perf to inject interrupts into KVM, and if BTS is added, another one
will be added. This may not end if more perf/kvm interactions are added.

In this patch set I merged Intel BTS with Intel PT's interrupt callbacks as
a first step, but better code could perhaps be tried in the future in two ways:

- Merge KVM's intel_pt codebase into the vPMU framework,  as the previous
  merging effort of guest intel pt is not fully discussed. vPMU will support as
  much as possible the time-sharing multiplexing of host and guest for PMU
  resources (including intel_pt) instead of static partion;
- There is one more, PMI interrupts after forcing KVM to exit, re-traveled
  host idt and assigned to the host handler, then called back to kvm, then
  injected to guest, if there is hardware support and KVM clear judgment,
  interrupts from guest can be injected directly into guest without going
  through the perf subsystem, which will save a lot of overhead.

I'm willing to share more to attract more developers, but the opinions
of the key players are probably more important to the future codebase.

Back to this BTS feature, if there are no blocked comments on this patchset,
more document, selftest and kvm-unit-test will follow obviously.

Like Xu (3):
  KVM + perf: Rename *_intel_pt_intr() for generic usage
  KVM + perf: Passing vector into generic perf_handle_guest_intr()
  KVM: x86/pmu: Add Intel Guest Branch Trace Store Support

 arch/x86/events/intel/bts.c     |  3 +++
 arch/x86/events/intel/core.c    |  2 +-
 arch/x86/include/asm/kvm_host.h |  8 +++++-
 arch/x86/kvm/pmu.h              |  3 +++
 arch/x86/kvm/vmx/capabilities.h |  7 ++++++
 arch/x86/kvm/vmx/vmx.c          | 43 +++++++++++++++++++++++++++------
 arch/x86/kvm/x86.c              |  2 +-
 include/linux/kvm_host.h        |  2 +-
 include/linux/perf_event.h      | 12 +++++----
 kernel/events/core.c            |  9 +++----
 virt/kvm/kvm_main.c             |  6 ++---
 11 files changed, 72 insertions(+), 25 deletions(-)

-- 
2.37.3

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ