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Message-ID: <202209270013.rVI9FMfT-lkp@intel.com>
Date: Tue, 27 Sep 2022 00:11:01 +0800
From: kernel test robot <lkp@...el.com>
To: Pali Rohár <pali@...nel.org>
Cc: llvm@...ts.linux.dev, kbuild-all@...ts.01.org,
linux-kernel@...r.kernel.org
Subject: [pali:pci-mvebu-pending 15/17]
drivers/pci/controller/pci-mvebu.c:1959:18: warning: format specifies type
'unsigned int' but the argument has type 'resource_size_t' (aka 'unsigned
long long')
tree: https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git pci-mvebu-pending
head: 9b3eff662c2d20d498b56210119e408df51289b3
commit: 1c4086274adc207b4ace4b833db22cf691f3b88f [15/17] PCI: mvebu: Add support for Orion PCIe controller
config: arm-buildonly-randconfig-r002-20220925
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git/commit/?id=1c4086274adc207b4ace4b833db22cf691f3b88f
git remote add pali https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git
git fetch --no-tags pali pci-mvebu-pending
git checkout 1c4086274adc207b4ace4b833db22cf691f3b88f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/pci/controller/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/pci-mvebu.c:1959:18: warning: format specifies type 'unsigned int' but the argument has type 'resource_size_t' (aka 'unsigned long long') [-Wformat]
port->name, resource_size(&port->cfg), pcie->cfg.end - pcie_cfg_offset + 1);
^~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^~~~~~~~~~~
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^~~~~~~~~~~
>> drivers/pci/controller/pci-mvebu.c:1959:45: warning: format specifies type 'unsigned int' but the argument has type 'unsigned long long' [-Wformat]
port->name, resource_size(&port->cfg), pcie->cfg.end - pcie_cfg_offset + 1);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^~~~~~~~~~~
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^~~~~~~~~~~
drivers/pci/controller/pci-mvebu.c:1146:34: warning: unused function 'sys_to_pcie' [-Wunused-function]
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
^
3 warnings generated.
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for TEGRA20_APB_DMA
Depends on [n]: DMADEVICES [=n] && (ARCH_TEGRA [=y] || COMPILE_TEST [=y])
Selected by [y]:
- SOC_TEGRA_FUSE [=y] && ARCH_TEGRA [=y] && ARCH_TEGRA_2x_SOC [=y]
vim +1959 drivers/pci/controller/pci-mvebu.c
1889
1890 static int mvebu_pcie_probe(struct platform_device *pdev)
1891 {
1892 struct device *dev = &pdev->dev;
1893 struct mvebu_pcie *pcie;
1894 struct pci_host_bridge *bridge;
1895 struct device_node *np = dev->of_node;
1896 struct device_node *child;
1897 phys_addr_t pcie_cfg_offset;
1898 int num, i, ret;
1899
1900 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
1901 if (!bridge)
1902 return -ENOMEM;
1903
1904 pcie = pci_host_bridge_priv(bridge);
1905 pcie->pdev = pdev;
1906 platform_set_drvdata(pdev, pcie);
1907
1908 ret = mvebu_pcie_parse_request_resources(pcie);
1909 if (ret)
1910 return ret;
1911
1912 pcie_cfg_offset = pcie->cfg.start;
1913
1914 num = of_get_available_child_count(np);
1915
1916 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
1917 if (!pcie->ports)
1918 return -ENOMEM;
1919
1920 i = 0;
1921 for_each_available_child_of_node(np, child) {
1922 struct mvebu_pcie_port *port = &pcie->ports[i];
1923
1924 ret = mvebu_pcie_parse_port(pcie, port, child);
1925 if (ret < 0) {
1926 of_node_put(child);
1927 return ret;
1928 } else if (ret == 0) {
1929 continue;
1930 }
1931
1932 port->dn = child;
1933 i++;
1934 }
1935 pcie->nports = i;
1936
1937 for (i = 0; i < pcie->nports; i++) {
1938 struct mvebu_pcie_port *port = &pcie->ports[i];
1939
1940 child = port->dn;
1941 if (!child)
1942 continue;
1943
1944 ret = mvebu_pcie_powerup(port);
1945 if (ret < 0)
1946 continue;
1947
1948 if (resource_size(&pcie->cfg) != 0) {
1949 unsigned int cfg_target, cfg_attr;
1950
1951 ret = mvebu_get_cfg_tgt_attr(child, pcie_cfg_offset, &port->cfg, &cfg_target, &cfg_attr);
1952 if (ret) {
1953 dev_err(dev, "%s: missing address range for cfg space\n", port->name);
1954 goto err_port_down;
1955 }
1956
1957 if (port->cfg.end > pcie->cfg.end) {
1958 dev_err(dev, "%s: requested cfg space of %u bytes is too large, available only %u bytes\n",
> 1959 port->name, resource_size(&port->cfg), pcie->cfg.end - pcie_cfg_offset + 1);
1960 port->cfg.start = port->cfg.end = 0;
1961 goto err_port_down;
1962 }
1963
1964 ret = mvebu_mbus_add_window_by_id(cfg_target, cfg_attr, port->cfg.start, resource_size(&port->cfg));
1965 if (ret) {
1966 dev_info(dev, "%s: cannot add mbus window for cfg space: %d\n", port->name, ret);
1967 port->cfg.start = port->cfg.end = 0;
1968 goto err_port_down;
1969 }
1970
1971 pcie_cfg_offset += resource_size(&port->cfg);
1972 }
1973
1974 port->base = mvebu_pcie_map_registers(pdev, child, port);
1975 if (IS_ERR(port->base)) {
1976 dev_err(dev, "%s: cannot map registers\n", port->name);
1977 port->base = NULL;
1978 goto err_port_down;
1979 }
1980
1981 ret = mvebu_pci_bridge_emul_init(port);
1982 if (ret < 0) {
1983 dev_err(dev, "%s: cannot init emulated bridge\n",
1984 port->name);
1985 goto err_base_unmap;
1986 }
1987
1988 if (port->error_irq > 0 || port->intx_irq > 0) {
1989 ret = mvebu_pcie_init_irq_domain(port);
1990 if (ret) {
1991 dev_err(dev, "%s: cannot init irq domain\n",
1992 port->name);
1993 goto err_bridge_cleanup;
1994 }
1995 }
1996
1997 if (port->error_irq > 0) {
1998 ret = devm_request_irq(dev, port->error_irq,
1999 mvebu_pcie_error_irq_handler,
2000 IRQF_SHARED | IRQF_NO_THREAD,
2001 port->name, port);
2002 if (ret) {
2003 dev_err(dev, "%s: cannot register error interrupt handler: %d\n",
2004 port->name, ret);
2005 goto err_domain_remove;
2006 }
2007 }
2008
2009 if (port->intx_irq > 0) {
2010 ret = devm_request_irq(dev, port->intx_irq,
2011 mvebu_pcie_intx_irq_handler,
2012 IRQF_SHARED | IRQF_NO_THREAD,
2013 port->name, port);
2014 if (ret) {
2015 dev_err(dev, "%s: cannot register intx interrupt handler: %d\n",
2016 port->name, ret);
2017 goto err_free_error_irq;
2018 }
2019 }
2020
2021 /*
2022 * Function mvebu_pcie_link_irq_handler() calls function
2023 * generic_handle_irq() and it expects local IRQs to be disabled
2024 * as normally generic_handle_irq() is called from the interrupt
2025 * context. So use TIMER_IRQSAFE flag for this link_irq_timer.
2026 * Available only if "error" interrupt was specified in DT.
2027 */
2028 if (port->error_irq > 0)
2029 timer_setup(&port->link_irq_timer,
2030 mvebu_pcie_link_irq_handler,
2031 TIMER_IRQSAFE);
2032
2033 /*
2034 * PCIe topology exported by mvebu hw is quite complicated. In
2035 * reality has something like N fully independent host bridges
2036 * where each host bridge has one PCIe Root Port (which acts as
2037 * PCI Bridge device). Each host bridge has its own independent
2038 * internal registers, independent access to PCI config space,
2039 * independent interrupt lines, independent window and memory
2040 * access configuration. But additionally there is some kind of
2041 * peer-to-peer support between PCIe devices behind different
2042 * host bridges limited just to forwarding of memory and I/O
2043 * transactions (forwarding of error messages and config cycles
2044 * is not supported). So we could say there are N independent
2045 * PCIe Root Complexes.
2046 *
2047 * For this kind of setup DT should have been structured into
2048 * N independent PCIe controllers / host bridges. But instead
2049 * structure in past was defined to put PCIe Root Ports of all
2050 * host bridges into one bus zero, like in classic multi-port
2051 * Root Complex setup with just one host bridge.
2052 *
2053 * This means that pci-mvebu.c driver provides "virtual" bus 0
2054 * on which registers all PCIe Root Ports (PCI Bridge devices)
2055 * specified in DT by their BDF addresses and virtually routes
2056 * PCI config access of each PCI bridge device to specific PCIe
2057 * host bridge.
2058 *
2059 * Normally PCI Bridge should choose between Type 0 and Type 1
2060 * config requests based on primary and secondary bus numbers
2061 * configured on the bridge itself. But because mvebu PCI Bridge
2062 * does not have registers for primary and secondary bus numbers
2063 * in its config space, it determinates type of config requests
2064 * via its own custom way.
2065 *
2066 * There are two options how mvebu determinate type of config
2067 * request.
2068 *
2069 * 1. If Secondary Bus Number Enable bit is not set or is not
2070 * available (applies for pre-XP PCIe controllers) then Type 0
2071 * is used if target bus number equals Local Bus Number (bits
2072 * [15:8] in register 0x1a04) and target device number differs
2073 * from Local Device Number (bits [20:16] in register 0x1a04).
2074 * Type 1 is used if target bus number differs from Local Bus
2075 * Number. And when target bus number equals Local Bus Number
2076 * and target device equals Local Device Number then request is
2077 * routed to Local PCI Bridge (PCIe Root Port).
2078 *
2079 * 2. If Secondary Bus Number Enable bit is set (bit 7 in
2080 * register 0x1a2c) then mvebu hw determinate type of config
2081 * request like compliant PCI Bridge based on primary bus number
2082 * which is configured via Local Bus Number (bits [15:8] in
2083 * register 0x1a04) and secondary bus number which is configured
2084 * via Secondary Bus Number (bits [7:0] in register 0x1a2c).
2085 * Local PCI Bridge (PCIe Root Port) is available on primary bus
2086 * as device with Local Device Number (bits [20:16] in register
2087 * 0x1a04).
2088 *
2089 * Secondary Bus Number Enable bit is disabled by default and
2090 * option 2. is not available on pre-XP PCIe controllers. Hence
2091 * this driver always use option 1.
2092 *
2093 * Basically it means that primary and secondary buses shares
2094 * one virtual number configured via Local Bus Number bits and
2095 * Local Device Number bits determinates if accessing primary
2096 * or secondary bus. Set Local Device Number to 1 and redirect
2097 * all writes of PCI Bridge Secondary Bus Number register to
2098 * Local Bus Number (bits [15:8] in register 0x1a04).
2099 *
2100 * So when accessing devices on buses behind secondary bus
2101 * number it would work correctly. And also when accessing
2102 * device 0 at secondary bus number via config space would be
2103 * correctly routed to secondary bus. Due to issues described
2104 * in mvebu_pcie_setup_hw(), PCI Bridges at primary bus (zero)
2105 * are not accessed directly via PCI config space but rarher
2106 * indirectly via kernel emulated PCI bridge driver.
2107 */
2108 mvebu_pcie_setup_hw(port);
2109 mvebu_pcie_set_local_dev_nr(port, 1);
2110 mvebu_pcie_set_local_bus_nr(port, 0);
2111
2112 continue;
2113
2114 err_free_error_irq:
2115 if (port->error_irq > 0)
2116 devm_free_irq(dev, port->error_irq, port);
2117
2118 err_domain_remove:
2119 if (port->intx_irq_domain)
2120 irq_domain_remove(port->intx_irq_domain);
2121
2122 if (port->rp_irq_domain)
2123 irq_domain_remove(port->rp_irq_domain);
2124
2125 err_bridge_cleanup:
2126 pci_bridge_emul_cleanup(&port->bridge);
2127
2128 err_base_unmap:
2129 devm_iounmap(dev, port->base);
2130 port->base = NULL;
2131
2132 err_port_down:
2133 if (port->cfg.end && resource_size(&port->cfg))
2134 mvebu_mbus_del_window(port->cfg.start, resource_size(&port->cfg));
2135
2136 mvebu_pcie_powerdown(port);
2137 }
2138
2139 bridge->sysdata = pcie;
2140 bridge->ops = &mvebu_pcie_ops;
2141 bridge->child_ops = &mvebu_pcie_child_ops;
2142 bridge->align_resource = mvebu_pcie_align_resource;
2143 bridge->map_irq = mvebu_pcie_map_irq;
2144
2145 return pci_host_probe(bridge);
2146 }
2147
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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