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Message-Id: <20220926180102.37614-4-amadeus@jmu.edu.cn>
Date: Tue, 27 Sep 2022 02:01:02 +0800
From: Chukun Pan <amadeus@....edu.cn>
To: linux.amoon@...il.com
Cc: heiko@...ech.de, krzysztof.kozlowski+dt@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
michael.riesch@...fvision.net, robh+dt@...nel.org,
Chukun Pan <amadeus@....edu.cn>
Subject: [PATCH 3/3] arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
Add Nodes to Radxa ROCK3 Model A board to support PCIe v3.
Signed-off-by: Chukun Pan <amadeus@....edu.cn>
---
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 1b195355da2a..458a12af1120 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -547,6 +547,19 @@ &pcie2x1 {
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ /* mPCIe slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_reset_h>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
@@ -583,6 +596,10 @@ pcie_enable_h: pcie-enable-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ minipcie_reset_h: minipcie-reset-h {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
ngffpcie_reset_h: ngffpcie-reset-h {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
--
2.25.1
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