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Message-Id: <1664269036-16142-10-git-send-email-hongxing.zhu@nxp.com>
Date: Tue, 27 Sep 2022 16:57:11 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: l.stach@...gutronix.de, bhelgaas@...gle.com, robh+dt@...nel.org,
lorenzo.pieralisi@....com, shawnguo@...nel.org, kishon@...com,
kw@...ux.com, frank.li@....com
Cc: hongxing.zhu@....com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: [PATCH v4 09/14] arm64: dts: Add i.MX8MP PCIe EP support on EVK board
Add i.MX8MP PCIe EP support on EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d..6daaa5ddc6b6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -390,6 +390,19 @@ &pcie {
status = "okay";
};
+&pcie_ep{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ status = "disabled";
+};
+
&snvs_pwrkey {
status = "okay";
};
--
2.25.1
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