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Message-ID: <OS0PR01MB5922BE73295E3562DC3FBA6E86549@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Date: Wed, 28 Sep 2022 07:02:29 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Prabhakar <prabhakar.csengg@...il.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
CC: Laurent Pinchart <laurent.pinchart@...asonboard.com>,
"linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [RFC PATCH 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD
clocks support PM
Hi Prabhakar,
> Subject: [RFC PATCH 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD
> clocks support PM
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> There are cases where not all CPG_MOD clocks should be assumed to
> support PM. For example on the CRU block there is a particular
> sequence that needs to be followed to initialize the CSI-2 D-PHY in
> which individual clocks need to be turned ON/OFF, due to which Runtime
> PM support wasn't used by the CRU CSI-2 driver.
>
> This patch adds support to allow indicating if PM is supported by the
> CPG_MOD clocks. A new macro is DEF_NO_PM() is added which sets the
> no_pm flag in struct rzg2l_mod_clk and when the driver uses Runtime PM
> support no_pm flag is checked to see if the clk needs to included as
> part of Runtime PM.
>
> CPG_MOD clocks with no_pm flag set need to be individually turned
> ON/OFF depending on the requirement of the driver.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> drivers/clk/renesas/rzg2l-cpg.c | 35 +++++++++++++++++++++++++++++---
> - drivers/clk/renesas/rzg2l-cpg.h | 12 ++++++++---
> 2 files changed, 40 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c
> b/drivers/clk/renesas/rzg2l-cpg.c index 3ff6ecd61756..d275324909e7
> 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -114,6 +114,8 @@ struct rzg2l_cpg_priv {
> struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; };
>
> +static struct rzg2l_cpg_priv *rzg2l_cpg_priv;
> +
> static void rzg2l_cpg_del_clk_provider(void *data) {
> of_clk_del_provider(data);
> @@ -1223,18 +1225,42 @@ static int
> rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
> return devm_reset_controller_register(priv->dev, &priv->rcdev);
> }
>
> +static inline const struct rzg2l_mod_clk *rzg2l_get_mod_clk(const
> +struct rzg2l_cpg_info *info, int id) {
> + unsigned int i;
> +
> + id += info->num_total_core_clks;
> + for (i = 0; i < info->num_mod_clks; i++) {
> + if (info->mod_clks[i].id == id)
> + return &info->mod_clks[i];
> + }
May be as an optimization add ID and clk to a separate list
and traverse that smaller list for DEF_NO_PM case.
case CPG_MOD:
return rzg2l_cpg_is_pm_mod(clkspec->args[1]);
Cheers,
Biju
> +
> + return NULL;
> +}
> +
> static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args
> *clkspec) {
> + struct rzg2l_cpg_priv *priv = rzg2l_cpg_priv;
> + const struct rzg2l_cpg_info *info = priv->info;
> + const struct rzg2l_mod_clk *mod_clk;
> +
> if (clkspec->args_count != 2)
> return false;
>
> - switch (clkspec->args[0]) {
> - case CPG_MOD:
> - return true;
> + if (clkspec->args[0] != CPG_MOD)
> + return false;
>
> - default:
> + if (clkspec->args[1] >= info->num_hw_mod_clks) {
> + dev_err(priv->dev, "Invalid clk index\n");
> return false;
> }
> +
> + mod_clk = rzg2l_get_mod_clk(info, clkspec->args[1]);
> + if (mod_clk && mod_clk->no_pm)
> + return false;
> +
> + return true;
> }
>
> static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused,
> struct device *dev) @@ -1348,6 +1374,7 @@ static int __init
> rzg2l_cpg_probe(struct platform_device *pdev)
> if (IS_ERR(priv->base))
> return PTR_ERR(priv->base);
>
> + rzg2l_cpg_priv = priv;
> nclks = info->num_total_core_clks + info->num_hw_mod_clks;
> clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
> if (!clks)
> diff --git a/drivers/clk/renesas/rzg2l-cpg.h
> b/drivers/clk/renesas/rzg2l-cpg.h index cecbdf5e4f93..1d68d3838392
> 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -176,6 +176,7 @@ enum clk_types {
> * @off: register offset
> * @bit: ON/MON bit
> * @is_coupled: flag to indicate coupled clock
> + * @no_pm: flag to indicate if clock doesn't support PM
> */
> struct rzg2l_mod_clk {
> const char *name;
> @@ -184,9 +185,10 @@ struct rzg2l_mod_clk {
> u16 off;
> u8 bit;
> bool is_coupled;
> + bool no_pm;
> };
>
> -#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
> +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled,
> _no_pm) \
> { \
> .name = _name, \
> .id = MOD_CLK_BASE + (_id), \
> @@ -194,13 +196,17 @@ struct rzg2l_mod_clk {
> .off = (_off), \
> .bit = (_bit), \
> .is_coupled = (_is_coupled), \
> + .no_pm = (_no_pm), \
> }
>
> #define DEF_MOD(_name, _id, _parent, _off, _bit) \
> - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
> + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false, false)
>
> #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
> - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
> + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true, false)
> +
> +#define DEF_NO_PM(_name, _id, _parent, _off, _bit) \
> + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false, true)
>
> /**
> * struct rzg2l_reset - Reset definitions
> --
> 2.25.1
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