linux-kernel - Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64

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Message-ID: <a20dc3ff-58e3-2fe2-f531-a2f55db35d4d@sequans.com>
Date:   Wed, 28 Sep 2022 12:04:38 +0200
From:   Valentin Korenblit <vkorenblit@...uans.com>
To:     Arnd Bergmann <arnd@...db.de>,
        Miquel Raynal <miquel.raynal@...tlin.com>
Cc:     kernel test robot <lkp@...el.com>, llvm@...ts.linux.dev,
        kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: Re: [mtd:nand/next 11/31]
 drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit
 declaration of function 'ioread64_rep' is invalid in C99


On 9/28/22 10:56, Arnd Bergmann wrote:
> On Wed, Sep 28, 2022, at 10:41 AM, Valentin Korenblit wrote:
>> On 9/27/22 22:02, Arnd Bergmann wrote:
>>> On Tue, Sep 27, 2022, at 4:56 PM, Valentin Korenblit wrote:
>>>>>> But in the mean time I am only half satisfied, because we plan to do
>>>>>> twice more accesses than needed _just_ because of a the COMPILE_TEST
>>>>>> constraint.
>>> It's also possible you have to read from the second word first,
>>> like
>>>
>>>     u32 *buf;
>>>     do {
>>>        buf[1] = __raw_readl(reg + 4);
>>>        buf[0] = __raw_readl(reg);
>>>        buf += 2;
>>>     }  while (buf < end);
>> Same result with pairs of readl at OFF0 and when reading at OFF1 first too,
>> I still see sdma_err. I've just opened a case to Cadence to see if there
>> is any workaround for this or if it is just not possible.
> I think this just means that the access has to be done with the exact
> width that is configured, and you cannot implement the access on
> 32-bit architectures. The only possibility is that you can reconfigure
> the nand controller to 32-bit mode at runtime, which is what Cadence
> should be able to tell you.
>
>      Arnd

I've just confirmed that we cannot change sdma width in runtime and
that sdma expects to be addressed in burst width, which is the bus
width (64-bit).

Valentin

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