linux-kernel - Re: [PATCH-next v1] arm64: dts: rockchip: Enable NVM Express PCIe controller on rock3a

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <ebb55252-f78b-e988-8a35-c41e6b6d7cda@arm.com>
Date:   Wed, 28 Sep 2022 11:37:54 +0100
From:   Robin Murphy <robin.murphy@....com>
To:     Chukun Pan <amadeus@....edu.cn>
Cc:     linux.amoon@...il.com, heiko@...ech.de, robh+dt@...nel.org,
        michael.riesch@...fvision.net, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH-next v1] arm64: dts: rockchip: Enable NVM Express PCIe
 controller on rock3a

On 2022-09-28 11:05, Chukun Pan wrote:
> Hi,
> 
> On 27-09-22, 18:47, Robin Murphy wrote:
> 
>> (as a side note, is pcie2x1's vpcie3v3-supply as queued in -next
>> actually correct? AFAICS the other socket is effectively powered
>> straight from VCC3V3_SYS so shouldn't have needed VCC3V3_PCIE,
>> but at least it's there now ready for this one)
> 
> Thanks for the correction, I didn't notice this before. You are right,
> the supply of pcie2x1 comes from VCC3V3_SYS. But if we change supply
> of pcie2x1 to VCC3V3_SYS, it will cause pcie30phy to fail to initialize
> normally. The error is the same as the following:
> 
>> phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock
>> failed 0x6890000, check input refclk and power supply
>> phy phy-fe8c0000.phy.4: phy init failed --> -110
>> rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110
> 
> If both vpcie3v3-supply of pcie2x1 and pcie3x2 use VCC3V3_PCIE like
> the vendor kernel, they can initialized normally.

Presumably that only works because you happen to be probing pcie2x1 
first, so it's not robust if that is disabled or probes later.

Looking again, it seems the answer was right there in the error message 
all along - the PCIe 3.0 phy wants its external reference clock 
describing correctly, and it's *that* clock which depends on 
VCC3V3_PI6C_03, which happens to be turned on in parallel with VCC3V3_PCIE.

Cheers,
Robin.