linux-kernel - [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <166444686053.401.11179384254910309532.tip-bot2@tip-bot2>
Date:   Thu, 29 Sep 2022 10:21:00 -0000
From:   "irqchip-bot for Apurva Nandan" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Apurva Nandan <a-nandan@...com>, Rob Herring <robh@...nel.org>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller:
 ti,sci-intr: Fix missing reg property in the binding

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     daa0b6d0187599a574cb5cb392b259bda3dcf979
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/daa0b6d0187599a574cb5cb392b259bda3dcf979
Author:        Apurva Nandan <a-nandan@...com>
AuthorDate:    Sat, 20 Aug 2022 00:37:29 +05:30
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Thu, 29 Sep 2022 11:13:43 +01:00

dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding

Fix the following warning in dtbs_check
interrupt-controller@...000: Unevaluated properties are not allowed ('reg' was unexpected)

Add the reg property in the schema.

Signed-off-by: Apurva Nandan <a-nandan@...com>
Acked-by: Rob Herring <robh@...nel.org>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20220819190729.32358-4-a-nandan@ti.com
---
 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
index e12aee4..c99cc73 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
@@ -58,6 +58,9 @@ properties:
         1 = If intr supports edge triggered interrupts.
         4 = If intr supports level triggered interrupts.
 
+  reg:
+    maxItems: 1
+
   interrupt-controller: true
 
   '#interrupt-cells':