linux-kernel - Re: [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property for PWM

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Message-ID: <7ae39c9c-8424-8b65-ac09-c0e87f3b0f01@arm.com>
Date:   Thu, 29 Sep 2022 16:50:43 +0100
From:   Robin Murphy <robin.murphy@....com>
To:     Johan Jonker <jbx6244@...il.com>, heiko@...ech.de
Cc:     thierry.reding@...il.com, u.kleine-koenig@...gutronix.de,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        sebastian.reichel@...labora.com, wxt@...k-chips.com,
        kever.yang@...k-chips.com, linux-pwm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH v1 2/2] ARM: dts: rk3288: add the interrupts property
 for PWM

On 2022-09-29 15:04, Johan Jonker wrote:
> The Rockchip rk3288 SoC has 4-built-in PWM channels.
> 
> Configurable to operate in capture mode.
> Measures the high/low polarity effective cycles of this input waveform
> Generates a single interrupt at the transition of input waveform polarity
> 
> Configurable to operate in continuous mode or one-shot mode.
> One-shot operation will produce N + 1 periods of the waveform,
> where N is the repeat counter value, and generates a single interrupt at
> the end of operation.
> Continuous mode generates the waveform continuously and
> do not generates any interrupts.
> 
> Add interrupts property to rk3288 PWM nodes.

As far as I can make out from the TRM, these are only valid when 
GRF_SOC_CON2[0] = 0, otherwise it's in "new" RK_PWM mode using SPI 78 
for all channels. Which apparently will be the case for anyone using 
upstream U-Boot:

https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-rockchip/rk3288/rk3288.c#L83

Thanks,
Robin.

> Signed-off-by: Caesar Wang <wxt@...k-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@...il.com>
> 
> ---
> 
> Original patch location:
>    ARM: dts: rk3288: add the interrupts property for PWM
>    https://github.com/rockchip-linux/kernel/commit/16b7b284618d1652e694f6286f575ce82f5f03e5
> 
> ---
> 
> "rockchip,rk3288-pwm" is in use as fall back string for Rockchip SoCs with combined
> PWM interrupt.
> ---
>   arch/arm/boot/dts/rk3288.dtsi | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 487b0e03d..1223aa369 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -675,6 +675,7 @@
>   	pwm0: pwm@...80000 {
>   		compatible = "rockchip,rk3288-pwm";
>   		reg = <0x0 0xff680000 0x0 0x10>;
> +		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>   		#pwm-cells = <3>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&pwm0_pin>;
> @@ -685,6 +686,7 @@
>   	pwm1: pwm@...80010 {
>   		compatible = "rockchip,rk3288-pwm";
>   		reg = <0x0 0xff680010 0x0 0x10>;
> +		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>   		#pwm-cells = <3>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&pwm1_pin>;
> @@ -695,6 +697,7 @@
>   	pwm2: pwm@...80020 {
>   		compatible = "rockchip,rk3288-pwm";
>   		reg = <0x0 0xff680020 0x0 0x10>;
> +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>   		#pwm-cells = <3>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&pwm2_pin>;
> @@ -705,6 +708,7 @@
>   	pwm3: pwm@...80030 {
>   		compatible = "rockchip,rk3288-pwm";
>   		reg = <0x0 0xff680030 0x0 0x10>;
> +		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>   		#pwm-cells = <3>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&pwm3_pin>;