linux-kernel - Re: [PATCH] dmaengine: sprd: Support two-stage dma interrupt

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Message-ID: <bd3ce49b-f887-1021-f21f-4e57ade1ba25@linux.alibaba.com>
Date:   Fri, 30 Sep 2022 14:42:28 +0800
From:   Baolin Wang <baolin.wang@...ux.alibaba.com>
To:     Cixi Geng <gengcixi@...il.com>, vkoul@...nel.org,
        orsonzhai@...il.com, zhang.lyra@...il.com
Cc:     dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dmaengine: sprd: Support two-stage dma interrupt

Hi Cixi,

On 9/30/2022 1:53 PM, Cixi Geng wrote:
> From: Cixi Geng <cixi.geng1@...soc.com>
> 
> Audio need to request Audio CP global dma interrupt, so Audio CP
> DMA should support two-stage interrupt to adapte it.
> It will occur interrupt when two-stage dma channel transfer done.

If the AP does not want the interrupt, why not just set SPRD_DMA_NO_INT?

I am struggling to understand the whole requirement, could you elaborate?

> 
> Signed-off-by: Cixi Geng <cixi.geng1@...soc.com>
> ---
>   drivers/dma/sprd-dma.c       |  8 ++++----
>   include/linux/dma/sprd-dma.h | 12 ++++++++++++
>   2 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c
> index 474d3ba8ec9f..7a9ade422a00 100644
> --- a/drivers/dma/sprd-dma.c
> +++ b/drivers/dma/sprd-dma.c
> @@ -441,7 +441,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
>   		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_SRC_CHN0_INT)
>   			val |= SPRD_DMA_GLB_SRC_INT;

That does not make sense to me. If user configues the interrupt type as 
SPRD_DMA_NO_INT, the code will still enable the source interrupt.

If user configures the interrupt type as SPRD_DMA_SRC_CHN0_INT, you will 
disable the source interrupt? Confusing...

>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> @@ -451,7 +451,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
>   		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_SRC_CHN1_INT)
>   			val |= SPRD_DMA_GLB_SRC_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> @@ -461,7 +461,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
>   			SPRD_DMA_GLB_DEST_CHN_MASK;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_DST_CHN0_INT)
>   			val |= SPRD_DMA_GLB_DEST_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> @@ -471,7 +471,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
>   			SPRD_DMA_GLB_DEST_CHN_MASK;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_DST_CHN1_INT)
>   			val |= SPRD_DMA_GLB_DEST_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h
> index d09c6f6f6da5..26de41d6d915 100644
> --- a/include/linux/dma/sprd-dma.h
> +++ b/include/linux/dma/sprd-dma.h
> @@ -101,6 +101,14 @@ enum sprd_dma_req_mode {
>    * is done.
>    * @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
>    * incorrect.
> + * @SPRD_DMA_SRC_CHN0_INT: interrupt occurred when source channel0
> + * transfer is done.
> + * @SPRD_DMA_SRC_CHN1_INT: interrupt occurred when source channel1
> + * transfer is done.
> + * @SPRD_DMA_DST_CHN0_INT: interrupt occurred when destination channel0
> + * transfer is done.
> + * @SPRD_DMA_DST_CHN1_INT: interrupt occurred when destination channel1
> + * transfer is done.
>    */
>   enum sprd_dma_int_type {
>   	SPRD_DMA_NO_INT,
> @@ -112,6 +120,10 @@ enum sprd_dma_int_type {
>   	SPRD_DMA_TRANS_BLK_INT,
>   	SPRD_DMA_LIST_INT,
>   	SPRD_DMA_CFGERR_INT,
> +	SPRD_DMA_SRC_CHN0_INT,
> +	SPRD_DMA_SRC_CHN1_INT,
> +	SPRD_DMA_DST_CHN0_INT,
> +	SPRD_DMA_DST_CHN1_INT,
>   };
>   
>   /*