| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <8f5f340d-9833-7f98-af73-be0f32a550cd@microchip.com>
Date: Fri, 30 Sep 2022 07:23:00 +0000
From: <Claudiu.Beznea@...rochip.com>
To: <Sergiu.Moga@...rochip.com>, <lee@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<Nicolas.Ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
<radu_nicolae.pirea@....ro>, <richard.genoud@...il.com>,
<gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
<Kavyasree.Kotagiri@...rochip.com>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<linux-serial@...r.kernel.org>
Subject: Re: [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the
existence of GCLK
On 22.09.2022 14:33, Sergiu Moga wrote:
> Previously, the atmel serial driver did not take into account the
> possibility of using the more customizable generic clock as its
> baudrate generator. Unless there is a Fractional Part available to
> increase accuracy, there is a high chance that we may be able to
> generate a baudrate closer to the desired one by using the GCLK as the
> clock source. Now, depending on the error rate between
> the desired baudrate and the actual baudrate, the serial driver will
> fallback on the generic clock. The generic clock must be provided
> in the DT node of the serial that may need a more flexible clock source.
>
> Furthermore, define the bit that represents the choice of having GCLK
> as a baudrate source clock inside the USCLKS bitmask of the Mode Register
> of USART IP's.
>
> Signed-off-by: Sergiu Moga <sergiu.moga@...rochip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
>
>
>
>
> v1 -> v2:
> - take into account the different placement of the baudrate clock source
> into the IP's Mode Register (USART vs UART)
> - don't check for atmel_port->gclk != NULL
> - use clk_round_rate instead of clk_set_rate + clk_get_rate
> - remove clk_disable_unprepare from the end of the probe method
>
>
>
> v2 -> v3:
> - add the error rate calculation function as an inline function instead of
> a macro definition
> - add `gclk_fail` goto
> - replace `goto err` with `goto err_clk_disable_unprepare;`
>
>
>
> v3 -> v4:
> - Nothing, this was previously [PATCH 14]
>
>
>
> v4 -> v5:
> - Squashed the previous
> `[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock`
> into this current commit
> - No more BRSRCCK bitmask as it is only 1 bit
>
>
>
> drivers/tty/serial/atmel_serial.c | 58 ++++++++++++++++++++++++++++++-
> drivers/tty/serial/atmel_serial.h | 1 +
> 2 files changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index acbf6b82d687..bd07f79a2df9 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -15,6 +15,7 @@
> #include <linux/init.h>
> #include <linux/serial.h>
> #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/console.h>
> #include <linux/sysrq.h>
> #include <linux/tty_flip.h>
> @@ -110,6 +111,7 @@ struct atmel_uart_char {
> struct atmel_uart_port {
> struct uart_port uart; /* uart */
> struct clk *clk; /* uart clock */
> + struct clk *gclk; /* uart generic clock */
> int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
> u32 backup_imr; /* IMR saved during suspend */
> int break_active; /* break being received */
> @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port)
> (port->iso7816.flags & SER_ISO7816_ENABLED);
> }
>
> +static inline int atmel_error_rate(int desired_value, int actual_value)
> +{
> + return 100 - (desired_value * 100) / actual_value;
> +}
> +
> #ifdef CONFIG_SERIAL_ATMEL_PDC
> static bool atmel_use_pdc_rx(struct uart_port *port)
> {
> @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
> * This is called on uart_close() or a suspend event.
> */
> clk_disable_unprepare(atmel_port->clk);
> + if (__clk_is_enabled(atmel_port->gclk))
> + clk_disable_unprepare(atmel_port->gclk);
> break;
> default:
> dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
> @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port,
> {
> struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
> unsigned long flags;
> - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
> + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
> + unsigned int baud, actual_baud, gclk_rate;
> + int ret;
>
> /* save the current mode register */
> mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
> @@ -2305,6 +2316,45 @@ static void atmel_set_termios(struct uart_port *port,
> cd = min_t(unsigned int, cd, ATMEL_US_CD);
> }
>
> + /*
> + * If there is no Fractional Part, there is a high chance that
> + * we may be able to generate a baudrate closer to the desired one
> + * if we use the GCLK as the clock source driving the baudrate
> + * generator.
> + */
> + if (!atmel_port->has_frac_baudrate) {
> + if (__clk_is_enabled(atmel_port->gclk))
> + clk_disable_unprepare(atmel_port->gclk);
> + gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
> + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
> + if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
> + abs(atmel_error_rate(baud, gclk_rate / 16))) {
> + clk_set_rate(atmel_port->gclk, 16 * baud);
> + ret = clk_prepare_enable(atmel_port->gclk);
> + if (ret)
> + goto gclk_fail;
> +
> + if (atmel_port->is_usart) {
> + mode &= ~ATMEL_US_USCLKS;
> + mode |= ATMEL_US_USCLKS_GCLK;
> + } else {
> + mode |= ATMEL_UA_BRSRCCK;
> + }
> +
> + /*
> + * Set the Clock Divisor for GCLK to 1.
> + * Since we were able to generate the smallest
> + * multiple of the desired baudrate times 16,
> + * then we surely can generate a bigger multiple
> + * with the exact error rate for an equally increased
> + * CD. Thus no need to take into account
> + * a higher value for CD.
> + */
> + cd = 1;
> + }
> + }
> +
> +gclk_fail:
> quot = cd | fp << ATMEL_US_FP_OFFSET;
>
> if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
> @@ -2900,6 +2950,12 @@ static int atmel_serial_probe(struct platform_device *pdev)
> if (ret)
> goto err;
>
> + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
> + if (IS_ERR(atmel_port->gclk)) {
> + ret = PTR_ERR(atmel_port->gclk);
> + goto err_clk_disable_unprepare;
> + }
> +
> ret = atmel_init_port(atmel_port, pdev);
> if (ret)
> goto err_clk_disable_unprepare;
> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
> index 2a525b58e11a..0fcadbeabc6c 100644
> --- a/drivers/tty/serial/atmel_serial.h
> +++ b/drivers/tty/serial/atmel_serial.h
> @@ -49,6 +49,7 @@
> #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */
> #define ATMEL_US_USCLKS_MCK (0 << 4)
> #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
> +#define ATMEL_US_USCLKS_GCLK (2 << 4)
> #define ATMEL_US_USCLKS_SCK (3 << 4)
> #define ATMEL_UA_FILTER BIT(4)
> #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */
Powered by blists - more mailing lists