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Date: Sat, 1 Oct 2022 22:35:03 +0800
From: kernel test robot <lkp@...el.com>
To: Hal Feng <hal.feng@...ux.starfivetech.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org
Cc: llvm@...ts.linux.dev, kbuild-all@...ts.01.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Linus Walleij <linus.walleij@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Hal Feng <hal.feng@...ux.starfivetech.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver
Hi Hal,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.0-rc7 next-20220930]
[cannot apply to clk/clk-next linusw-pinctrl/devel pza/reset/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 987a926c1d8a40e4256953b04771fbdb63bc7938
config: riscv-buildonly-randconfig-r006-20220926
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/9ef892ebb8b08cc65ab165f4962864e12b5c216d
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Hal-Feng/Basic-StarFive-JH7110-RISC-V-SoC-support/20220930-202655
git checkout 9ef892ebb8b08cc65ab165f4962864e12b5c216d
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash drivers/pinctrl/starfive/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/pinctrl/starfive/pinctrl-starfive.c:462:51: warning: variable 'value' is uninitialized when used here [-Wuninitialized]
ret = info->starfive_iopad_sel_func(pdev, pctl, value);
^~~~~
drivers/pinctrl/starfive/pinctrl-starfive.c:397:11: note: initialize the variable 'value' to silence this warning
u32 value;
^
= 0
drivers/pinctrl/starfive/pinctrl-starfive.c:32:1: warning: unused function 'starfive_pinctrl_find_group_by_name' [-Wunused-function]
starfive_pinctrl_find_group_by_name(struct pinctrl_dev *pctldev,
^
2 warnings generated.
vim +/value +462 drivers/pinctrl/starfive/pinctrl-starfive.c
386
387 int starfive_pinctrl_probe(struct platform_device *pdev,
388 const struct starfive_pinctrl_soc_info *info)
389 {
390 struct device *dev = &pdev->dev;
391 struct pinctrl_desc *starfive_pinctrl_desc;
392 struct starfive_pinctrl *pctl;
393 struct resource *res;
394 struct reset_control *rst;
395 struct clk *clk;
396 int ret, i;
397 u32 value;
398
399 if (!info || !info->pins || !info->npins) {
400 dev_err(&pdev->dev, "wrong pinctrl info\n");
401 return -EINVAL;
402 }
403
404 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
405 if (!pctl)
406 return -ENOMEM;
407
408 pctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
409 sizeof(*pctl->pin_regs),
410 GFP_KERNEL);
411 if (!pctl->pin_regs)
412 return -ENOMEM;
413
414 for (i = 0; i < info->npins; i++) {
415 pctl->pin_regs[i].io_conf_reg = -1;
416 pctl->pin_regs[i].gpo_dout_reg = -1;
417 pctl->pin_regs[i].gpo_doen_reg = -1;
418 pctl->pin_regs[i].func_sel_reg = -1;
419 pctl->pin_regs[i].syscon_reg = -1;
420 pctl->pin_regs[i].pad_sel_reg = -1;
421 }
422
423 pctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "control");
424 if (IS_ERR(pctl->padctl_base))
425 return PTR_ERR(pctl->padctl_base);
426
427 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
428 if (res) {
429 pctl->gpio_base = devm_ioremap_resource(dev, res);
430 if (IS_ERR(pctl->gpio_base))
431 return PTR_ERR(pctl->gpio_base);
432 }
433
434 clk = devm_clk_get_optional(dev, NULL);
435 if (IS_ERR(clk))
436 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
437
438 rst = devm_reset_control_get_exclusive(dev, NULL);
439 if (IS_ERR(rst))
440 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
441
442 if (clk) {
443 ret = clk_prepare_enable(clk);
444 if (ret)
445 return dev_err_probe(dev, ret, "could not enable clock\n");
446
447 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
448 if (ret)
449 return ret;
450 }
451
452 /*
453 * We don't want to assert reset and risk undoing pin muxing for the
454 * early boot serial console, but let's make sure the reset line is
455 * deasserted in case someone runs a really minimal bootloader.
456 */
457 ret = reset_control_deassert(rst);
458 if (ret)
459 return dev_err_probe(dev, ret, "could not deassert reset\n");
460
461 if (info->starfive_iopad_sel_func) {
> 462 ret = info->starfive_iopad_sel_func(pdev, pctl, value);
463 if (ret)
464 return ret;
465 }
466
467 starfive_pinctrl_desc = devm_kzalloc(&pdev->dev,
468 sizeof(*starfive_pinctrl_desc),
469 GFP_KERNEL);
470 if (!starfive_pinctrl_desc)
471 return -ENOMEM;
472
473 raw_spin_lock_init(&pctl->lock);
474
475 starfive_pinctrl_desc->name = dev_name(&pdev->dev);
476 starfive_pinctrl_desc->pins = info->pins;
477 starfive_pinctrl_desc->npins = info->npins;
478 starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
479 starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
480 starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
481 starfive_pinctrl_desc->owner = THIS_MODULE;
482
483 mutex_init(&pctl->mutex);
484
485 pctl->info = info;
486 pctl->dev = &pdev->dev;
487 platform_set_drvdata(pdev, pctl);
488 pctl->gc.parent = dev;
489 ret = devm_pinctrl_register_and_init(&pdev->dev,
490 starfive_pinctrl_desc, pctl,
491 &pctl->pctl_dev);
492 if (ret) {
493 dev_err(&pdev->dev,
494 "could not register starfive pinctrl driver\n");
495 return ret;
496 }
497
498 ret = pinctrl_enable(pctl->pctl_dev);
499 if (ret) {
500 dev_err(&pdev->dev,
501 "pin controller failed to start\n");
502 return ret;
503 }
504
505 if (info->starfive_gpio_register) {
506 ret = info->starfive_gpio_register(pdev, pctl);
507 if (ret) {
508 dev_err(&pdev->dev,
509 "starfive_gpio_register failed to register\n");
510 return ret;
511 }
512 }
513
514 return 0;
515 }
516 EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
517
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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