linux-kernel - Re: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable private data

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Date:   Mon, 3 Oct 2022 04:00:23 +0000
From:   CK Hu (胡俊光) <ck.hu@...iatek.com>
To:     Yongqiang Niu (牛永强) 
        <yongqiang.niu@...iatek.com>,
        "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>
CC:     "jassisinghbrar@...il.com" <jassisinghbrar@...il.com>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "hsinyi@...omium.org" <hsinyi@...omium.org>
Subject: Re: [PATCH v8, 1/4] mailbox: mtk-cmdq: add gce software ddr enable
 private data

Hi, Yongqiang:

On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> if gce work control by software, we need set software enable
> for MT8186 Soc
> 
> there is a handshake flow between gce and ddr hardware,
> if not set ddr enable flag of gce, ddr will fall into idle
> mode, then gce instructions will not process done.
> we need set this flag of gce to tell ddr when gce is idle or busy
> controlled by software flow.
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9465f9081515..88db6b4642db 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -38,6 +38,8 @@
>  #define CMDQ_THR_PRIORITY		0x40
>  
>  #define GCE_GCTL_VALUE			0x48
> +#define GCE_CTRL_BY_SW				GENMASK(2, 0)
> +#define GCE_DDR_EN				GENMASK(18, 16)
>  
>  #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
>  #define CMDQ_THR_ENABLED		0x1
> @@ -80,6 +82,7 @@ struct cmdq {
>  	bool			suspended;
>  	u8			shift_pa;
>  	bool			control_by_sw;
> +	bool			sw_ddr_en;
>  	u32			gce_num;
>  };
>  
> @@ -87,6 +90,7 @@ struct gce_plat {
>  	u32 thread_nr;
>  	u8 shift;
>  	bool control_by_sw;
> +	bool sw_ddr_en;
>  	u32 gce_num;
>  };
>  
> @@ -130,6 +134,10 @@ static void cmdq_init(struct cmdq *cmdq)
>  	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
>  	if (cmdq->control_by_sw)
>  		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> +
> +	if (cmdq->sw_ddr_en)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> GCE_GCTL_VALUE);

I think 0x48[18:16] and 0x48[2:0] control different things and fix
different problem. So for this patch, you should just control
0x48[18:16] and the code would be:

if (cmdq->sw_ddr_en) {
	reg = readl(cmdq->base + GCE_GCTL_VALUE);
	reg |= GCE_DDR_EN;
	writel(reg, cmdq->base + GCE_GCTL_VALUE);
}

Regards,
CK

> +
>  	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base +
> CMDQ_THR_SLOT_CYCLES);
>  	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
>  		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> @@ -543,6 +551,7 @@ static int cmdq_probe(struct platform_device
> *pdev)
>  	cmdq->thread_nr = plat_data->thread_nr;
>  	cmdq->shift_pa = plat_data->shift;
>  	cmdq->control_by_sw = plat_data->control_by_sw;
> +	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
>  	cmdq->gce_num = plat_data->gce_num;
>  	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
>  	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler,
> IRQF_SHARED,