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Date: Mon, 3 Oct 2022 13:24:53 +0800 From: Richard Zhu <hongxing.zhu@....com> To: vkoul@...nel.org, a.fatoum@...gutronix.de, p.zabel@...gutronix.de, l.stach@...gutronix.de, bhelgaas@...gle.com, lorenzo.pieralisi@....com, robh@...nel.org, shawnguo@...nel.org, alexander.stein@...tq-group.com, marex@...x.de, richard.leitner@...ux.dev Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, kernel@...gutronix.de, linux-imx@....com, Richard Zhu <hongxing.zhu@....com> Subject: [PATCH v11 2/4] phy: freescale: imx8m-pcie: Refine register definitions No function changes, refine PHY register definitions. - Keep align with other CMN PHY registers, refine the definitions of PHY_CMN_REG75. - Remove two BIT definitions that are not used at all. Signed-off-by: Richard Zhu <hongxing.zhu@....com> Signed-off-by: Lucas Stach <l.stach@...gutronix.de> Tested-by: Marek Vasut <marex@...x.de> Tested-by: Richard Leitner <richard.leitner@...data.com> Tested-by: Alexander Stein <alexander.stein@...tq-group.com> Reviewed-by: Lucas Stach <l.stach@...gutronix.de> --- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c index ad7d2edfc414..2377ed307b53 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -31,12 +31,10 @@ #define IMX8MM_PCIE_PHY_CMN_REG065 0x194 #define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) #define ANA_AUX_TX_LVL GENMASK(3, 0) -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4 +#define ANA_PLL_DONE 0x3 #define PCIE_PHY_TRSV_REG5 0x414 -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D #define PCIE_PHY_TRSV_REG6 0x418 -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) @@ -131,9 +129,8 @@ static int imx8_pcie_phy_init(struct phy *phy) reset_control_deassert(imx8_phy->reset); /* Polling to check the phy is ready or not. */ - ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, - val, val == PCIE_PHY_CMN_REG75_PLL_DONE, - 10, 20000); + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075, + val, val == ANA_PLL_DONE, 10, 20000); return ret; } -- 2.25.1
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