linux-kernel - Re: [PATCH V1] PCI: dwc: Use dev_info for PCIe link down event logging

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Message-ID: <27e8f2e8-8b97-a142-9da4-437c8dd498c4@nvidia.com>
Date:   Mon, 3 Oct 2022 16:55:16 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Bjorn Helgaas <helgaas@...nel.org>
Cc:     Jon Hunter <jonathanh@...dia.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Krzysztof Wilczynski <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Thierry Reding <treding@...dia.com>,
        PCI <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Krishna Thota <kthota@...dia.com>,
        Manikanta Maddireddy <mmaddireddy@...dia.com>,
        sagar.tv@...il.com,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH V1] PCI: dwc: Use dev_info for PCIe link down event
 logging

Hi Bjorn / Lorenzo,
Just checking if there are any more comments for this patch? If not, are 
we good to take it?

Thanks,
Vidya Sagar

On 9/26/2022 3:59 PM, Vidya Sagar wrote:
> Hi,
> Just checking if we are good with this patch or does it need any further 
> modifications?
> 
> Thanks,
> Vidya Sagar
> 
> On 9/15/2022 8:22 PM, Manivannan Sadhasivam wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Thu, Sep 15, 2022 at 09:16:27AM -0500, Rob Herring wrote:
>>> On Wed, Sep 14, 2022 at 1:24 AM Manivannan Sadhasivam
>>> <manivannan.sadhasivam@...aro.org> wrote:
>>>>
>>>> On Tue, Sep 13, 2022 at 03:07:46PM -0500, Bjorn Helgaas wrote:
>>>>> On Tue, Sep 13, 2022 at 06:00:30PM +0100, Jon Hunter wrote:
>>>>>> On 13/09/2022 17:51, Manivannan Sadhasivam wrote:
>>>>>>> On Tue, Sep 13, 2022 at 03:42:37PM +0530, Vidya Sagar wrote:
>>>>>>>> Some of the platforms (like Tegra194 and Tegra234) have open 
>>>>>>>> slots and
>>>>>>>> not having an endpoint connected to the slot is not an error.
>>>>>>>> So, changing the macro from dev_err to dev_info to log the event.
>>>>>>>
>>>>>>> But the link up not happening is an actual error and -ETIMEDOUT 
>>>>>>> is being
>>>>>>> returned. So I don't think the log severity should be changed.
>>>>>>
>>>>>> Yes it is an error in the sense it is a timeout, but reporting an 
>>>>>> error
>>>>>> because nothing is attached to a PCI slot seems a bit noisy. 
>>>>>> Please note
>>>>>> that a similar change was made by the following commit and it also 
>>>>>> seems
>>>>>> appropriate here ...
>>>>>>
>>>>>> commit 4b16a8227907118e011fb396022da671a52b2272
>>>>>> Author: Manikanta Maddireddy <mmaddireddy@...dia.com>
>>>>>> Date:   Tue Jun 18 23:32:06 2019 +0530
>>>>>>
>>>>>>      PCI: tegra: Change link retry log level to debug
>>>>>>
>>>>>>
>>>>>> BTW, we check for error messages in the dmesg output and this is a 
>>>>>> new error
>>>>>> seen as of Linux v6.0 and so this was flagged in a test. We can 
>>>>>> ignore the
>>>>>> error, but in this case it seem more appropriate to make this a 
>>>>>> info or
>>>>>> debug level print.
>>>>>
>>>>> Can you tell whether there's a device present, e.g., via Slot Status
>>>>> Presence Detect?  If there's nothing in the slot, I don't know why we
>>>>> would print anything at all.  If a card is present but there's no
>>>>> link, that's probably worthy of dev_info() or even dev_err().
>>>>>
>>>>
>>>> I don't think all form factors allow for the PRSNT pin to be wired up,
>>>> so we cannot know if the device is actually present in the slot or 
>>>> not all
>>>> the time. Maybe we should do if the form factor supports it?
>>>>
>>>>> I guess if you can tell the slot is empty, there's no point in even
>>>>> trying to start the link, so you could avoid both the message and the
>>>>> timeout by not even calling dw_pcie_wait_for_link().
>>>>
>>>> Right. There is an overhead of waiting for ~1ms during boot.
>>>
>>> Async probe should mitigate that, right? Saravana is working toward
>>> making that the default instead of opt in, but you could opt in now.
>>>
>>
>> No. The delay is due to the DWC core waiting for link up that depends on
>> the PCIe device to be present on the slot. The driver probe order
>> doesn't apply here.
>>
>> Thanks,
>> Mani
>>
>>> Rob