lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <6bcf2f53-ffd1-5159-47a5-b3d7db548158@collabora.com>
Date:   Mon, 3 Oct 2022 16:54:14 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Yongqiang Niu <yongqiang.niu@...iatek.com>,
        CK Hu <ck.hu@...iatek.com>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>
Cc:     Jassi Brar <jassisinghbrar@...il.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Hsin-Yi Wang <hsinyi@...omium.org>
Subject: Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support
 flow

Il 30/09/22 18:06, Yongqiang Niu ha scritto:
> add gce ddr enable control flow when gce suspend/resume
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> ---
>   drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 04eb44d89119..2db82ff838ed 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -94,6 +94,18 @@ struct gce_plat {
>   	u32 gce_num;
>   };
>   
> +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> +{
> +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> +
> +	if (enable)
> +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);

My only concern here is about the previous value stored in the GCE_GCTL_VALUE
register, as you're overwriting it in its entirety with
GCE_DDR_EN | GCE_CTRL_BY_SW.

Can you guarantee that this register is not pre-initialized with some value,
and that these are the only bits to be `1` in this register?

Otherwise, you will have to readl and modify the bits instead... by the way,
if this register doesn't get any changes during runtime, you may cache it
at probe time to avoid reading it for every suspend/resume operation.

Regards,
Angelo


Powered by blists - more mailing lists