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Date: Mon, 3 Oct 2022 11:30:02 -0500
From: Rob Herring <robh@...nel.org>
To: Trevor Wu <trevor.wu@...iatek.com>
Cc: broonie@...nel.org, tiwai@...e.com, matthias.bgg@...il.com,
p.zabel@...gutronix.de, alsa-devel@...a-project.org,
linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH 10/12] dt-bindings: mediatek: mt8188: add audio afe
document
On Fri, Sep 30, 2022 at 10:56:59PM +0800, Trevor Wu wrote:
> Add mt8188 audio afe document.
>
> Signed-off-by: Trevor Wu <trevor.wu@...iatek.com>
> ---
> .../bindings/sound/mt8188-afe-pcm.yaml | 202 ++++++++++++++++++
> 1 file changed, 202 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml
> new file mode 100644
> index 000000000000..50d53c5d59ad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/mt8188-afe-pcm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek AFE PCM controller for mt8188
> +
> +maintainers:
> + - Trevor Wu <trevor.wu@...iatek.com>
> +
> +properties:
> + compatible:
> + const: mediatek,mt8188-audio
If the block is called 'AFE PCM controller', then perhaps use some of
that for the name instead of just 'audio'.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: audiosys
> +
> + memory-region:
> + maxItems: 1
> + description: |
> + Shared memory region for AFE memif. A "shared-dma-pool".
> + See ../reserved-memory/reserved-memory.txt for details.
What does that file contain?
No need to provide generic descriptions of common properties, so the
reference can just be dropped.
> +
> + mediatek,topckgen:
> + $ref: "/schemas/types.yaml#/definitions/phandle"
Don't need quotes.
> + description: The phandle of the mediatek topckgen controller
> +
> + mediatek,infracfg:
> + $ref: "/schemas/types.yaml#/definitions/phandle"
> + description: The phandle of the mediatek infracfg controller
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: 26M clock
> + - description: audio pll1 clock
> + - description: audio pll2 clock
> + - description: clock divider for i2si1_mck
> + - description: clock divider for i2si2_mck
> + - description: clock divider for i2so1_mck
> + - description: clock divider for i2so2_mck
> + - description: clock divider for dptx_mck
> + - description: a1sys hoping clock
> + - description: audio intbus clock
> + - description: audio hires clock
> + - description: audio local bus clock
> + - description: mux for dptx_mck
> + - description: mux for i2so1_mck
> + - description: mux for i2so2_mck
> + - description: mux for i2si1_mck
> + - description: mux for i2si2_mck
> + - description: audio 26m clock
> +
> + clock-names:
> + items:
> + - const: clk26m
> + - const: apll1_ck
> + - const: apll2_ck
> + - const: apll12_div0
> + - const: apll12_div1
> + - const: apll12_div2
> + - const: apll12_div3
> + - const: apll12_div9
> + - const: a1sys_hp_sel
> + - const: aud_intbus_sel
> + - const: audio_h_sel
> + - const: audio_local_bus_sel
> + - const: dptx_m_sel
> + - const: i2so1_m_sel
> + - const: i2so2_m_sel
> + - const: i2si1_m_sel
> + - const: i2si2_m_sel
> + - const: adsp_audio26m
> +
> + mediatek,etdm-in1-chn-disabled:
> + $ref: /schemas/types.yaml#/definitions/uint8-array
> + maxItems: 16
> + description: Specify which input channel should be disabled.
What value disables/enables?
items:
enum: [ ??? ]
> +
> + mediatek,etdm-in2-chn-disabled:
> + $ref: /schemas/types.yaml#/definitions/uint8-array
> + maxItems: 16
> + description: Specify which input channel should be disabled.
> +
> +patternProperties:
> + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
> + description: Specify etdm in mclk output rate for always on case.
> +
> + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
> + description: Specify etdm out mclk output rate for always on case.
> +
> + "^mediatek,etdm-in[1-2]-multi-pin-mode$":
> + type: boolean
> + description: if present, the etdm data mode is I2S.
> +
> + "^mediatek,etdm-out[1-3]-multi-pin-mode$":
> + type: boolean
> + description: if present, the etdm data mode is I2S.
> +
> + "^mediatek,etdm-in[1-2]-cowork-source$":
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + etdm modules can share the same external clock pin. Specify
> + which etdm clock source is required by this etdm in moudule.
> + enum:
> + - 0 # etdm1_in
> + - 1 # etdm2_in
> + - 2 # etdm1_out
> + - 3 # etdm2_out
> +
> + "^mediatek,etdm-out[1-2]-cowork-source$":
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + etdm modules can share the same external clock pin. Specify
> + which etdm clock source is required by this etdm out moudule.
> + enum:
> + - 0 # etdm1_in
> + - 1 # etdm2_in
> + - 2 # etdm1_out
> + - 3 # etdm2_out
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - resets
> + - reset-names
> + - mediatek,topckgen
> + - mediatek,infracfg
> + - power-domains
> + - clocks
> + - clock-names
> + - memory-region
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + afe: afe@...10000 {
> + compatible = "mediatek,mt8188-audio";
> + reg = <0x10b10000 0x10000>;
> + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 14>;
> + reset-names = "audiosys";
> + mediatek,topckgen = <&topckgen>;
> + mediatek,infracfg = <&infracfg_ao>;
> + power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
> + memory-region = <&snd_dma_mem_reserved>;
> + clocks = <&clk26m>,
> + <&topckgen 72>, //CLK_TOP_APLL1
> + <&topckgen 73>, //CLK_TOP_APLL2
> + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
> + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
> + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
> + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
> + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
> + <&topckgen 83>, //CLK_TOP_A1SYS_HP
> + <&topckgen 31>, //CLK_TOP_AUD_INTBUS
> + <&topckgen 32>, //CLK_TOP_AUDIO_H
> + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
> + <&topckgen 81>, //CLK_TOP_DPTX
> + <&topckgen 77>, //CLK_TOP_I2SO1
> + <&topckgen 78>, //CLK_TOP_I2SO2
> + <&topckgen 79>, //CLK_TOP_I2SI1
> + <&topckgen 80>, //CLK_TOP_I2SI2
> + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
> + clock-names = "clk26m",
> + "apll1_ck",
> + "apll2_ck",
> + "apll12_div0",
> + "apll12_div1",
> + "apll12_div2",
> + "apll12_div3",
> + "apll12_div9",
> + "a1sys_hp_sel",
> + "aud_intbus_sel",
> + "audio_h_sel",
> + "audio_local_bus_sel",
> + "dptx_m_sel",
> + "i2so1_m_sel",
> + "i2so2_m_sel",
> + "i2si1_m_sel",
> + "i2si2_m_sel",
> + "adsp_audio_26m";
> + };
> +
> +...
> --
> 2.18.0
>
>
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