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Message-Id: <20221004203724.1459763-1-heiko@sntech.de>
Date: Tue, 4 Oct 2022 22:37:22 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: atishp@...shpatra.org, anup@...infault.org, will@...nel.org,
mark.rutland@....com, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Conor.Dooley@...rochip.com, cmuellner@...ux.com,
samuel@...lland.org, Heiko Stuebner <heiko@...ech.de>
Subject: [PATCH v4 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension
but not completely identical, so this series
changes in v4:
- add new patch to cache sbi mvendor, march and mimp-ids (Atish)
- errata dependencies in one line (Conor)
- make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish)
changes in v3:
- improve commit message (Atish, Conor)
- IS_ENABLED and BIT() in errata probe (Conor)
The change depends on my cpufeature/t-head errata probe cleanup series [1].
changes in v2:
- use alternatives for the CSR access
- make the irq num selection a bit nicer
There is of course a matching opensbi-part whose most recent implementation
can be found on [0].
[0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@sntech.de
[1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@sntech.de/
Heiko Stuebner (2):
RISC-V: Cache SBI vendor values
drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head
C9xx cores
arch/riscv/Kconfig.erratas | 13 +++++++++++
arch/riscv/errata/thead/errata.c | 18 +++++++++++++++
arch/riscv/include/asm/errata_list.h | 16 +++++++++++++-
arch/riscv/kernel/sbi.c | 21 +++++++++++++++---
drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++---------
5 files changed, 87 insertions(+), 14 deletions(-)
--
2.35.1
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