linux-kernel - [tip: timers/core] clocksource/drivers/imx-sysctr: handle nxp,no-divider property

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Message-ID: <166487562691.401.3433013681547293513.tip-bot2@tip-bot2>
Date:   Tue, 04 Oct 2022 09:27:06 -0000
From:   "tip-bot2 for Peng Fan" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Peng Fan <peng.fan@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: timers/core] clocksource/drivers/imx-sysctr: handle
 nxp,no-divider property

The following commit has been merged into the timers/core branch of tip:

Commit-ID:     27b30995b75d1e79360c164ba179bca86ab76ba6
Gitweb:        https://git.kernel.org/tip/27b30995b75d1e79360c164ba179bca86ab76ba6
Author:        Peng Fan <peng.fan@....com>
AuthorDate:    Fri, 02 Sep 2022 19:12:07 +08:00
Committer:     Daniel Lezcano <daniel.lezcano@...aro.org>
CommitterDate: Tue, 20 Sep 2022 10:49:46 +02:00

clocksource/drivers/imx-sysctr: handle nxp,no-divider property

The previous hardware design embedds a internal divider for base clock.
New design not has that divider, so check the nxp,no-divider property,
if true, directly use base clock input, otherwise divide by 3 as before.

Signed-off-by: Peng Fan <peng.fan@....com>
Link: https://lore.kernel.org/r/20220902111207.2902493-3-peng.fan@oss.nxp.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
---
 drivers/clocksource/timer-imx-sysctr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index 523e376..5a7a951 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -134,8 +134,10 @@ static int __init sysctr_timer_init(struct device_node *np)
 	if (ret)
 		return ret;
 
-	/* system counter clock is divided by 3 internally */
-	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+	if (!of_property_read_bool(np, "nxp,no-divider")) {
+		/* system counter clock is divided by 3 internally */
+		to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+	}
 
 	sys_ctr_base = timer_of_base(&to_sysctr);
 	cmpcr = readl(sys_ctr_base + CMPCR);