| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 4 Oct 2022 11:37:30 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Trevor Wu <trevor.wu@...iatek.com>, broonie@...nel.org,
tiwai@...e.com, robh+dt@...nel.org, matthias.bgg@...il.com,
p.zabel@...gutronix.de
Cc: alsa-devel@...a-project.org, linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH 04/12] ASoC: mediatek: mt8188: support adda in platform
driver
Il 30/09/22 16:56, Trevor Wu ha scritto:
> Add mt8188 adda dai driver support.
>
> Signed-off-by: Trevor Wu <trevor.wu@...iatek.com>
> ---
> sound/soc/mediatek/mt8188/mt8188-dai-adda.c | 639 ++++++++++++++++++++
> 1 file changed, 639 insertions(+)
> create mode 100644 sound/soc/mediatek/mt8188/mt8188-dai-adda.c
>
> diff --git a/sound/soc/mediatek/mt8188/mt8188-dai-adda.c b/sound/soc/mediatek/mt8188/mt8188-dai-adda.c
> new file mode 100644
> index 000000000000..ba8f622bb107
> --- /dev/null
> +++ b/sound/soc/mediatek/mt8188/mt8188-dai-adda.c
> @@ -0,0 +1,639 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek ALSA SoC Audio DAI ADDA Control
> + *
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Bicycle Tsai <bicycle.tsai@...iatek.com>
> + * Trevor Wu <trevor.wu@...iatek.com>
> + * Chun-Chia Chiu <chun-chia.chiu@...iatek.com>
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/regmap.h>
> +#include "mt8188-afe-clk.h"
> +#include "mt8188-afe-common.h"
> +#include "mt8188-reg.h"
> +
> +#define ADDA_HIRES_THRES 48000
> +
> +enum {
> + SUPPLY_SEQ_CLOCK_SEL,
> + SUPPLY_SEQ_ADDA_DL_ON,
> + SUPPLY_SEQ_ADDA_MTKAIF_CFG,
> + SUPPLY_SEQ_ADDA_UL_ON,
> + SUPPLY_SEQ_ADDA_AFE_ON,
> +};
> +
> +enum {
> + MTK_AFE_ADDA_DL_RATE_8K = 0,
> + MTK_AFE_ADDA_DL_RATE_11K = 1,
> + MTK_AFE_ADDA_DL_RATE_12K = 2,
> + MTK_AFE_ADDA_DL_RATE_16K = 3,
> + MTK_AFE_ADDA_DL_RATE_22K = 4,
> + MTK_AFE_ADDA_DL_RATE_24K = 5,
> + MTK_AFE_ADDA_DL_RATE_32K = 6,
> + MTK_AFE_ADDA_DL_RATE_44K = 7,
> + MTK_AFE_ADDA_DL_RATE_48K = 8,
> + MTK_AFE_ADDA_DL_RATE_96K = 9,
> + MTK_AFE_ADDA_DL_RATE_192K = 10,
> +};
> +
> +enum {
> + MTK_AFE_ADDA_UL_RATE_8K = 0,
> + MTK_AFE_ADDA_UL_RATE_16K = 1,
> + MTK_AFE_ADDA_UL_RATE_32K = 2,
> + MTK_AFE_ADDA_UL_RATE_48K = 3,
> + MTK_AFE_ADDA_UL_RATE_96K = 4,
> + MTK_AFE_ADDA_UL_RATE_192K = 5,
> +};
> +
> +enum {
> + DELAY_DATA_MISO1 = 0,
> + DELAY_DATA_MISO0 = 1,
> +};
> +
> +struct mtk_dai_adda_priv {
> + unsigned int dl_rate;
> + unsigned int ul_rate;
> +};
> +
..snip..
> +
> +static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe)
> +{
> + struct mt8188_afe_private *afe_priv = afe->platform_priv;
> + struct mtkaif_param *param = &afe_priv->mtkaif_params;
> + int delay_data;
> + int delay_cycle;
> + unsigned int mask = 0;
> + unsigned int val = 0;
> +
> + /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
> + mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
> + val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
> +
> + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
This should be
regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
> +
> + mask = RG_RX_PROTOCOL2;
> + val = RG_RX_PROTOCOL2;
> + regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
regmap_set_bits() again
> +
> + if (!param->mtkaif_calibration_ok) {
> + dev_info(afe->dev, "%s(), calibration fail\n", __func__);
> + return 0;
> + }
> +
> + /* set delay for ch1, ch2 */
> + if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >=
> + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) {
> + delay_data = DELAY_DATA_MISO1;
> + delay_cycle =
> + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] -
> + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1];
> + } else {
> + delay_data = DELAY_DATA_MISO0;
> + delay_cycle =
> + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] -
> + param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0];
> + }
> +
> + val = 0;
> + mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
> + val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
> + MTKAIF_RXIF_DELAY_CYCLE_MASK;
val = FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle);
> + val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data);
Can you please use bitfield access macros across the entire file (and the others)?
This will both increase human readability and add compile-time checks on register
fields.
> + regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
> +
> + return 0;
> +}
> +
> +static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol,
> + int event)
> +{
> + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> +
> + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
> + __func__, w->name, event);
> +
> + switch (event) {
> + case SND_SOC_DAPM_PRE_PMU:
> + mt8188_adda_mtkaif_init(afe);
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol,
> + int event)
> +{
> + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> +
> + dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
> + __func__, w->name, event);
> +
> + switch (event) {
> + case SND_SOC_DAPM_POST_PMD:
> + /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
> + usleep_range(125, 135);
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic)
> +{
> + unsigned int reg = AFE_ADDA_UL_SRC_CON0;
> + unsigned int val = 0;
> + unsigned int mask;
> +
> + mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
> + UL_MODE_3P25M_CH2_CTL);
val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | UL_MODE_3P25M_CH2_CTL);
> +
> + /* turn on dmic, ch1, ch2 */
> + if (dmic)
regmap_set_bits(afe->regmap, reg, val);
else
regmap_clear_bits(afe->regmap, reg, val);
> + val = mask;
> +
> + regmap_update_bits(afe->regmap, reg, mask, val);
> +}
> +
..snip..
> +
> +static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,
> + struct snd_soc_dapm_widget *sink)
> +{
> + struct snd_soc_dapm_widget *w = source;
> + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> + struct mt8188_afe_private *afe_priv = afe->platform_priv;
> + struct mtk_dai_adda_priv *adda_priv;
> +
> + adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA];
> +
> + if (!adda_priv) {
> + dev_err(afe->dev, "%s adda_priv == NULL", __func__);
> + return 0;
return -EINVAL?
> + }
> +
> + return (adda_priv->ul_rate > ADDA_HIRES_THRES) ? 1 : 0;
return !!(adda_priv->ul_rate > ADDA_HIRES_THRES);
> +}
> +
> +static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source,
> + struct snd_soc_dapm_widget *sink)
> +{
> + struct snd_soc_dapm_widget *w = source;
> + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> + struct mt8188_afe_private *afe_priv = afe->platform_priv;
> + struct mtk_dai_adda_priv *adda_priv;
> +
> + adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA];
> +
> + if (!adda_priv) {
> + dev_err(afe->dev, "%s adda_priv == NULL", __func__);
> + return 0;
same here
> + }
> +
> + return (adda_priv->dl_rate > ADDA_HIRES_THRES) ? 1 : 0;
> +}
> +
..snip..
Regards,
Angelo
Powered by blists - more mailing lists