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Message-ID: <ca836507-50ca-13bc-ef88-7f69b1333c99@linux.intel.com>
Date: Tue, 4 Oct 2022 20:28:07 -0700
From: Sathyanarayanan Kuppuswamy
<sathyanarayanan.kuppuswamy@...ux.intel.com>
To: Bjorn Helgaas <helgaas@...nel.org>, linux-pci@...r.kernel.org
Cc: Vidya Sagar <vidyas@...dia.com>,
"Saheed O . Bolarinwa" <refactormyself@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rajat Jain <rajatja@...gle.com>,
"Kenneth R . Crudup" <kenny@...ix.com>,
Kai-Heng Feng <kai.heng.feng@...onical.com>,
Abhishek Sahu <abhsahu@...dia.com>,
Thierry Reding <treding@...dia.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Krishna Thota <kthota@...dia.com>,
Manikanta Maddireddy <mmaddireddy@...dia.com>,
Vidya Sagar <sagar.tv@...il.com>, sagupta@...dia.com,
linux-kernel@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH 0/3] PCI/ASPM: Fix L1SS issues
On 10/4/22 7:58 PM, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@...gle.com>
>
> This is really late, but I think we have two significant issues with L1SS:
>
> 1) pcie_aspm_cap_init() reads from the L1SS capability even when it
> doesn't exist, so it reads PCI_COMMAND and PCI_STATUS instead and treats
> those as an L1SS Capability value.
>
> 2) encode_l12_threshold() encodes LTR_L1.2_THRESHOLD as smaller than
> requested, so ports may enter L1.2 when they should not.
>
> These patches are intended to fix both issues.
Looks good to me.
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>
> Bjorn Helgaas (3):
> PCI/ASPM: Factor out L1 PM Substates configuration
> PCI/ASPM: Ignore L1 PM Substates if device lacks capability
> PCI/ASPM: Correct LTR_L1.2_THRESHOLD computation
>
> drivers/pci/pcie/aspm.c | 155 +++++++++++++++++++++++-----------------
> 1 file changed, 90 insertions(+), 65 deletions(-)
>
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
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