linux-kernel - Re: [PATCH RESEND v5 1/1] clk: mstar: msc313 cpupll clk driver

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Message-ID: <CABgxDoLPMPP2zzrGbxrtKS6SgqQW3-u=jSZRnCF_sRs766ifsw@mail.gmail.com>
Date:   Wed, 5 Oct 2022 09:35:20 +0200
From:   Romain Perier <romain.perier@...il.com>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Daniel Palmer <daniel@...f.com>,
        Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Willy Tarreau <w@....eu>
Subject: Re: [PATCH RESEND v5 1/1] clk: mstar: msc313 cpupll clk driver

Hi,

Le ven. 30 sept. 2022 à 21:17, Stephen Boyd <sboyd@...nel.org> a écrit :
>
> Quoting Romain Perier (2022-06-03 12:05:09)
> > From: Daniel Palmer <daniel@...f.com>
> >
> > Add a driver for the CPU pll/ARM pll/MIPS pll that is present
> > in MStar SoCs.
> >
> > Currently there is no documentation for this block so it's possible
> > this driver isn't entirely correct.
> >
> > Only tested on the version of this IP in the MStar/SigmaStar
> > ARMv7 SoCs.
> >
> > Co-authored-by: Willy Tarreau <w@....eu>
>
> This is not a standard tag, maybe Co-developed-by is what you want? A
> Signed-off-by tag should be here from Willy Tarreau then.
>
> > Signed-off-by: Daniel Palmer <daniel@...f.com>
>
> Your Signed-off-by needs to be here. I can't apply this otherwise.
>
> > diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig
> > index de37e1bce2d2..146eeb637318 100644
> > --- a/drivers/clk/mstar/Kconfig
> > +++ b/drivers/clk/mstar/Kconfig
> > @@ -1,4 +1,11 @@
> >  # SPDX-License-Identifier: GPL-2.0-only
> > +config MSTAR_MSC313_CPUPLL
> > +       bool "MStar CPUPLL driver"
> > +       depends on ARCH_MSTARV7 || COMPILE_TEST
> > +       default ARCH_MSTARV7
> > +       help
> > +         Support for the CPU PLL present on MStar/Sigmastar SoCs.
> > +
> >  config MSTAR_MSC313_MPLL
> >         bool "MStar MPLL driver"
> >         depends on ARCH_MSTARV7 || COMPILE_TEST
> > @@ -7,3 +14,4 @@ config MSTAR_MSC313_MPLL
> >         help
> >           Support for the MPLL PLL and dividers block present on
> >           MStar/Sigmastar SoCs.
> > +
> > diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile
> > index f8dcd25ede1d..21296a04e65a 100644
> > --- a/drivers/clk/mstar/Makefile
> > +++ b/drivers/clk/mstar/Makefile
> > @@ -2,5 +2,5 @@
> >  #
> >  # Makefile for mstar specific clk
> >  #
> > -
> > +obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o
> >  obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o
> > diff --git a/drivers/clk/mstar/clk-msc313-cpupll.c b/drivers/clk/mstar/clk-msc313-cpupll.c
> > new file mode 100644
> > index 000000000000..c57b509e8c20
> > --- /dev/null
> > +++ b/drivers/clk/mstar/clk-msc313-cpupll.c
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 Daniel Palmer <daniel@...ngy.jp>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
>
> Ought to include kernel.h and device.h too.
>
> > +
> [...]
> > +
> > +static const struct clk_ops msc313_cpupll_ops = {
> > +       .recalc_rate    = msc313_cpupll_recalc_rate,
> > +       .round_rate     = msc313_cpupll_round_rate,
> > +       .set_rate       = msc313_cpupll_set_rate,
> > +};
> > +
> > +static const struct of_device_id msc313_cpupll_of_match[] = {
> > +       { .compatible = "mstar,msc313-cpupll" },
> > +       {}
> > +};
> > +
> > +static const struct clk_parent_data cpupll_parent = {
>
> Why not put this on the stack? It doesn't have to live forever.
>
> > +       .index  = 0,
> > +};
> > +
> > +static int msc313_cpupll_probe(struct platform_device *pdev)
> > +{
> > +       struct clk_init_data clk_init = {};
> > +       struct device *dev = &pdev->dev;
> > +       struct msc313_cpupll *cpupll;
> > +       int ret;
> > +
> > +       cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL);
> > +       if (!cpupll)
> > +               return -ENOMEM;
> > +
> > +       cpupll->base = devm_platform_ioremap_resource(pdev, 0);
> > +       if (IS_ERR(cpupll->base))
> > +               return PTR_ERR(cpupll->base);
> > +
> > +       /* LPF might not contain the current frequency so fix that up */
> > +       msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L,
> > +                                 msc313_cpupll_reg_read32(cpupll, REG_CURRENT));
> > +
> > +       clk_init.name = dev_name(dev);
> > +       clk_init.ops = &msc313_cpupll_ops;
> > +       clk_init.parent_data = &cpupll_parent;
> > +       clk_init.num_parents = 1;
> > +       cpupll->clk_hw.init = &clk_init;
> > +
> > +       ret = devm_clk_hw_register(dev, &cpupll->clk_hw);
> > +       if (ret)
> > +               return ret;
> > +
> > +       return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, &cpupll->clk_hw);
>
> Use devm to add the provider too.


Ok, it does not seem to be huge to change, I will send another iteration.

Thanks,
Cheers,
Romain