linux-kernel - Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver

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Date:   Wed, 5 Oct 2022 10:52:24 +0000
From:   Rahul Tanwar <rtanwar@...linear.com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>
CC:     linux-lgm-soc <linux-lgm-soc@...linear.com>,
        Yi xin Zhu <yzhu@...linear.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from
 clk driver

[Resend due to mail delivery failure in earlier reply - one email id got 
corrupted somehow in earlier reply]

Hi Stephen,

On 30/9/2022 9:01 am, Stephen Boyd wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> Quoting Rahul Tanwar (2022-09-28 22:45:59)
>> On 29/9/2022 8:17 am, Stephen Boyd wrote:
>>> This email was sent from outside of MaxLinear.
>>>
>>>
>>> Quoting Rahul Tanwar (2022-09-21 23:24:26)
>>>> In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled
>>>> from EPU (power management IP) in certain power saving modes. If gate
>>>> clocks are allowed to be enabled/disabled from CGU clk driver, then
>>>> there arises a conflict where in case clk driver disables a gate clk,
>>>> and then EPU tries to disable the same gate clk, then it will hang
>>>> polling for the clk gated successful status.
>>>
>>> Is there any point in registering these clks when they're not supposed
>>> to be controlled from Linux?
>>
>>
>> As mentioned in the full commit log, only reason to register these clks
>> is to be backward compatible with older versions of similar SoC's which
>> reuse the same clk CGU IP but do not use same power management IP. Such
>> older SoCs also use the same clk driver and for them these clks are
>> required to be controlled by clk ops from Linux.
>>
> 
> Why is the clk driver probing on the new SoCs? Is it providing
> something? Can we detect that the power management IP exists and not
> register these clks?
> 

We discussed in the team about not registering gate clks at all as you
mentioned. But if we do that, all peripheral drivers that use these clks
would need modifications so their probe does not fail due to failure
returns of clk related standard calls for e.g devm_clk_get(),
clk_prepare_enable(). These are standard calls in probe for all the
drivers and a lot of them use gate clks. So this would need a lot of
changes with possibility of breaking working functionalities.

Also, i incorrectly mentioned about the reason being backward
compatibility with older SoCs. Main reason is to support different power
profiles use cases as per end product requirements some of which might
control it from clk framework i.e. this driver. We keep a internal
driver flag just for this purpose to provide this flexibility depending
on the use case which is what we have used here.

I am sending v3 with more clear & correct description about it to
justify the need for these changes.

Thanks,
Rahul

>