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Message-ID: <CAA8EJpr=0w0KReqNW2jP8DzvXLgo_o6bKmwMOed2sXb6d8HKhg@mail.gmail.com>
Date: Wed, 5 Oct 2022 22:31:43 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Marijn Suijten <marijn.suijten@...ainline.org>
Cc: phone-devel@...r.kernel.org, Rob Clark <robdclark@...il.com>,
Vinod Koul <vkoul@...nel.org>,
~postmarketos/upstreaming@...ts.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
Daniel Vetter <daniel@...ll.ch>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>,
Thomas Zimmermann <tzimmermann@...e.de>,
Javier Martinez Canillas <javierm@...hat.com>,
Alex Deucher <alexander.deucher@....com>,
Douglas Anderson <dianders@...omium.org>,
Vladimir Lypak <vladimir.lypak@...il.com>,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, freedreno@...ts.freedesktop.org,
David Airlie <airlied@...ux.ie>
Subject: Re: [PATCH v2 5/7] drm/msm/dsi: Account for DSC's bits_per_pixel
having 4 fractional bits
On Wed, 5 Oct 2022 at 21:17, Marijn Suijten
<marijn.suijten@...ainline.org> wrote:
>
> drm_dsc_config's bits_per_pixel field holds a fractional value with 4
> bits, which all panel drivers should adhere to for
> drm_dsc_pps_payload_pack() to generate a valid payload. All code in the
> DSI driver here seems to assume that this field doesn't contain any
> fractional bits, hence resulting in the wrong values being computed.
> Since none of the calculations leave any room for fractional bits or
> seem to indicate any possible area of support, disallow such values
> altogether.
>
> Fixes: b9080324d6ca ("drm/msm/dsi: add support for dsc data")
> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 25 +++++++++++++++++--------
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index f42794cdd4c1..4717d49d76be 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -33,7 +33,7 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> -static int dsi_populate_dsc_params(struct drm_dsc_config *dsc);
> +static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
>
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> @@ -908,6 +908,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> u32 va_end = va_start + mode->vdisplay;
> u32 hdisplay = mode->hdisplay;
> u32 wc;
> + int ret;
>
> DBG("");
>
> @@ -943,7 +944,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> /* we do the calculations for dsc parameters here so that
> * panel can use these parameters
> */
> - dsi_populate_dsc_params(dsc);
> + ret = dsi_populate_dsc_params(msm_host, dsc);
> + if (ret)
> + return;
>
> /* Divide the display by 3 but keep back/font porch and
> * pulse width same
> @@ -1769,7 +1772,7 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> };
>
> -static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> +static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
> {
> int mux_words_size;
> int groups_per_line, groups_total;
> @@ -1780,6 +1783,12 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> int data;
> int final_value, final_scale;
> int i;
> + u16 bpp = dsc->bits_per_pixel >> 4;
> +
> + if (dsc->bits_per_pixel & 0xf) {
> + DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
> + return -EINVAL;
> + }
>
> dsc->rc_model_size = 8192;
> dsc->first_line_bpg_offset = 12;
> @@ -1801,7 +1810,7 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> }
>
> dsc->initial_offset = 6144; /* Not bpp 12 */
> - if (dsc->bits_per_pixel != 8)
> + if (bpp != 8)
> dsc->initial_offset = 2048; /* bpp = 12 */
>
> mux_words_size = 48; /* bpc == 8/10 */
> @@ -1824,14 +1833,14 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> * params are calculated
> */
> groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
> - dsc->slice_chunk_size = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
> + dsc->slice_chunk_size = DIV_ROUND_UP(dsc->slice_width * bpp, 8);
I'd still prefer if we can get closer to drm_dsc_compute_rc_parameters().
The mentioned function has the following code:
vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
vdsc_cfg->bits_per_pixel,
(8 * 16));
In fact, could you please take a look if we can switch to using this
function and drop our code?
>
> /* rbs-min */
> min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
> - dsc->initial_xmit_delay * dsc->bits_per_pixel +
> + dsc->initial_xmit_delay * bpp +
> groups_per_line * dsc->first_line_bpg_offset;
>
> - hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, bpp);
>
> dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
>
> @@ -1854,7 +1863,7 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
> data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
> dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
>
> - data = dsc->initial_xmit_delay * dsc->bits_per_pixel;
> + data = dsc->initial_xmit_delay * bpp;
> final_value = dsc->rc_model_size - data + num_extra_mux_bits;
> dsc->final_offset = final_value;
>
> --
> 2.38.0
>
--
With best wishes
Dmitry
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