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Message-ID: <202210061101.qhJWmyqG-lkp@intel.com>
Date: Thu, 6 Oct 2022 11:45:15 +0800
From: kernel test robot <lkp@...el.com>
To: Rodrigo Siqueira <Rodrigo.Siqueira@....com>
Cc: llvm@...ts.linux.dev, kbuild-all@...ts.01.org,
linux-kernel@...r.kernel.org,
Alex Deucher <alexander.deucher@....com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:1004:15:
warning: variable 'dppclk_delay_subtotal' set but not used
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 833477fce7a14d43ae4c07f8ddc32fa5119471a2
commit: af2f2a256e048f1b83605eaae49948e4a6811ac1 drm/amd/display: Enable dlg and vba compilation for dcn314
date: 3 weeks ago
config: x86_64-buildonly-randconfig-r005-20221003
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=af2f2a256e048f1b83605eaae49948e4a6811ac1
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout af2f2a256e048f1b83605eaae49948e4a6811ac1
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:1004:15: warning: variable 'dppclk_delay_subtotal' set but not used [-Wunused-but-set-variable]
unsigned int dppclk_delay_subtotal;
^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:1005:15: warning: variable 'dispclk_delay_subtotal' set but not used [-Wunused-but-set-variable]
unsigned int dispclk_delay_subtotal;
^
2 warnings generated.
vim +/dppclk_delay_subtotal +1004 drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c
41529d79ce1655 Roman Li 2022-06-28 934
41529d79ce1655 Roman Li 2022-06-28 935 // Note: currently taken in as is.
41529d79ce1655 Roman Li 2022-06-28 936 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
41529d79ce1655 Roman Li 2022-06-28 937 static void dml_rq_dlg_get_dlg_params(
41529d79ce1655 Roman Li 2022-06-28 938 struct display_mode_lib *mode_lib,
41529d79ce1655 Roman Li 2022-06-28 939 const display_e2e_pipe_params_st *e2e_pipe_param,
41529d79ce1655 Roman Li 2022-06-28 940 const unsigned int num_pipes,
41529d79ce1655 Roman Li 2022-06-28 941 const unsigned int pipe_idx,
41529d79ce1655 Roman Li 2022-06-28 942 display_dlg_regs_st *disp_dlg_regs,
41529d79ce1655 Roman Li 2022-06-28 943 display_ttu_regs_st *disp_ttu_regs,
41529d79ce1655 Roman Li 2022-06-28 944 const display_rq_dlg_params_st *rq_dlg_param,
41529d79ce1655 Roman Li 2022-06-28 945 const display_dlg_sys_params_st *dlg_sys_param,
41529d79ce1655 Roman Li 2022-06-28 946 const bool cstate_en,
41529d79ce1655 Roman Li 2022-06-28 947 const bool pstate_en,
41529d79ce1655 Roman Li 2022-06-28 948 const bool vm_en,
41529d79ce1655 Roman Li 2022-06-28 949 const bool ignore_viewport_pos,
41529d79ce1655 Roman Li 2022-06-28 950 const bool immediate_flip_support)
41529d79ce1655 Roman Li 2022-06-28 951 {
41529d79ce1655 Roman Li 2022-06-28 952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
41529d79ce1655 Roman Li 2022-06-28 953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
41529d79ce1655 Roman Li 2022-06-28 954 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
41529d79ce1655 Roman Li 2022-06-28 955 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
41529d79ce1655 Roman Li 2022-06-28 956 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
41529d79ce1655 Roman Li 2022-06-28 957 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
41529d79ce1655 Roman Li 2022-06-28 958 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
41529d79ce1655 Roman Li 2022-06-28 959
41529d79ce1655 Roman Li 2022-06-28 960 // -------------------------
41529d79ce1655 Roman Li 2022-06-28 961 // Section 1.15.2.1: OTG dependent Params
41529d79ce1655 Roman Li 2022-06-28 962 // -------------------------
41529d79ce1655 Roman Li 2022-06-28 963 // Timing
41529d79ce1655 Roman Li 2022-06-28 964 unsigned int htotal = dst->htotal;
41529d79ce1655 Roman Li 2022-06-28 965 unsigned int hblank_end = dst->hblank_end;
41529d79ce1655 Roman Li 2022-06-28 966 unsigned int vblank_start = dst->vblank_start;
41529d79ce1655 Roman Li 2022-06-28 967 unsigned int vblank_end = dst->vblank_end;
41529d79ce1655 Roman Li 2022-06-28 968
41529d79ce1655 Roman Li 2022-06-28 969 double dppclk_freq_in_mhz = clks->dppclk_mhz;
41529d79ce1655 Roman Li 2022-06-28 970 double refclk_freq_in_mhz = clks->refclk_mhz;
41529d79ce1655 Roman Li 2022-06-28 971 double pclk_freq_in_mhz = dst->pixel_rate_mhz;
41529d79ce1655 Roman Li 2022-06-28 972 bool interlaced = dst->interlaced;
41529d79ce1655 Roman Li 2022-06-28 973 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
41529d79ce1655 Roman Li 2022-06-28 974 double min_ttu_vblank;
41529d79ce1655 Roman Li 2022-06-28 975 unsigned int dlg_vblank_start;
41529d79ce1655 Roman Li 2022-06-28 976 bool dual_plane;
41529d79ce1655 Roman Li 2022-06-28 977 bool mode_422;
41529d79ce1655 Roman Li 2022-06-28 978 unsigned int access_dir;
41529d79ce1655 Roman Li 2022-06-28 979 unsigned int vp_height_l;
41529d79ce1655 Roman Li 2022-06-28 980 unsigned int vp_width_l;
41529d79ce1655 Roman Li 2022-06-28 981 unsigned int vp_height_c;
41529d79ce1655 Roman Li 2022-06-28 982 unsigned int vp_width_c;
41529d79ce1655 Roman Li 2022-06-28 983
41529d79ce1655 Roman Li 2022-06-28 984 // Scaling
41529d79ce1655 Roman Li 2022-06-28 985 unsigned int htaps_l;
41529d79ce1655 Roman Li 2022-06-28 986 unsigned int htaps_c;
41529d79ce1655 Roman Li 2022-06-28 987 double hratio_l;
41529d79ce1655 Roman Li 2022-06-28 988 double hratio_c;
41529d79ce1655 Roman Li 2022-06-28 989 double vratio_l;
41529d79ce1655 Roman Li 2022-06-28 990 double vratio_c;
41529d79ce1655 Roman Li 2022-06-28 991 bool scl_enable;
41529d79ce1655 Roman Li 2022-06-28 992
41529d79ce1655 Roman Li 2022-06-28 993 unsigned int swath_width_ub_l;
41529d79ce1655 Roman Li 2022-06-28 994 unsigned int dpte_groups_per_row_ub_l;
41529d79ce1655 Roman Li 2022-06-28 995 unsigned int swath_width_ub_c;
41529d79ce1655 Roman Li 2022-06-28 996 unsigned int dpte_groups_per_row_ub_c;
41529d79ce1655 Roman Li 2022-06-28 997
41529d79ce1655 Roman Li 2022-06-28 998 unsigned int meta_chunks_per_row_ub_l;
41529d79ce1655 Roman Li 2022-06-28 999 unsigned int meta_chunks_per_row_ub_c;
41529d79ce1655 Roman Li 2022-06-28 1000 unsigned int vupdate_offset;
41529d79ce1655 Roman Li 2022-06-28 1001 unsigned int vupdate_width;
41529d79ce1655 Roman Li 2022-06-28 1002 unsigned int vready_offset;
41529d79ce1655 Roman Li 2022-06-28 1003
41529d79ce1655 Roman Li 2022-06-28 @1004 unsigned int dppclk_delay_subtotal;
41529d79ce1655 Roman Li 2022-06-28 @1005 unsigned int dispclk_delay_subtotal;
41529d79ce1655 Roman Li 2022-06-28 1006
41529d79ce1655 Roman Li 2022-06-28 1007 unsigned int vstartup_start;
41529d79ce1655 Roman Li 2022-06-28 1008 unsigned int dst_x_after_scaler;
41529d79ce1655 Roman Li 2022-06-28 1009 unsigned int dst_y_after_scaler;
41529d79ce1655 Roman Li 2022-06-28 1010 double dst_y_prefetch;
41529d79ce1655 Roman Li 2022-06-28 1011 double dst_y_per_vm_vblank;
41529d79ce1655 Roman Li 2022-06-28 1012 double dst_y_per_row_vblank;
41529d79ce1655 Roman Li 2022-06-28 1013 double dst_y_per_vm_flip;
41529d79ce1655 Roman Li 2022-06-28 1014 double dst_y_per_row_flip;
41529d79ce1655 Roman Li 2022-06-28 1015 double max_dst_y_per_vm_vblank;
41529d79ce1655 Roman Li 2022-06-28 1016 double max_dst_y_per_row_vblank;
41529d79ce1655 Roman Li 2022-06-28 1017 double vratio_pre_l;
41529d79ce1655 Roman Li 2022-06-28 1018 double vratio_pre_c;
41529d79ce1655 Roman Li 2022-06-28 1019 unsigned int req_per_swath_ub_l;
41529d79ce1655 Roman Li 2022-06-28 1020 unsigned int req_per_swath_ub_c;
41529d79ce1655 Roman Li 2022-06-28 1021 unsigned int meta_row_height_l;
41529d79ce1655 Roman Li 2022-06-28 1022 unsigned int meta_row_height_c;
41529d79ce1655 Roman Li 2022-06-28 1023 unsigned int swath_width_pixels_ub_l;
41529d79ce1655 Roman Li 2022-06-28 1024 unsigned int swath_width_pixels_ub_c;
41529d79ce1655 Roman Li 2022-06-28 1025 unsigned int scaler_rec_in_width_l;
41529d79ce1655 Roman Li 2022-06-28 1026 unsigned int scaler_rec_in_width_c;
41529d79ce1655 Roman Li 2022-06-28 1027 unsigned int dpte_row_height_l;
41529d79ce1655 Roman Li 2022-06-28 1028 unsigned int dpte_row_height_c;
41529d79ce1655 Roman Li 2022-06-28 1029 double hscale_pixel_rate_l;
41529d79ce1655 Roman Li 2022-06-28 1030 double hscale_pixel_rate_c;
41529d79ce1655 Roman Li 2022-06-28 1031 double min_hratio_fact_l;
41529d79ce1655 Roman Li 2022-06-28 1032 double min_hratio_fact_c;
41529d79ce1655 Roman Li 2022-06-28 1033 double refcyc_per_line_delivery_pre_l;
41529d79ce1655 Roman Li 2022-06-28 1034 double refcyc_per_line_delivery_pre_c;
41529d79ce1655 Roman Li 2022-06-28 1035 double refcyc_per_line_delivery_l;
41529d79ce1655 Roman Li 2022-06-28 1036 double refcyc_per_line_delivery_c;
41529d79ce1655 Roman Li 2022-06-28 1037
41529d79ce1655 Roman Li 2022-06-28 1038 double refcyc_per_req_delivery_pre_l;
41529d79ce1655 Roman Li 2022-06-28 1039 double refcyc_per_req_delivery_pre_c;
41529d79ce1655 Roman Li 2022-06-28 1040 double refcyc_per_req_delivery_l;
41529d79ce1655 Roman Li 2022-06-28 1041 double refcyc_per_req_delivery_c;
41529d79ce1655 Roman Li 2022-06-28 1042
41529d79ce1655 Roman Li 2022-06-28 1043 unsigned int full_recout_width;
41529d79ce1655 Roman Li 2022-06-28 1044 double refcyc_per_req_delivery_pre_cur0;
41529d79ce1655 Roman Li 2022-06-28 1045 double refcyc_per_req_delivery_cur0;
41529d79ce1655 Roman Li 2022-06-28 1046 double refcyc_per_req_delivery_pre_cur1;
41529d79ce1655 Roman Li 2022-06-28 1047 double refcyc_per_req_delivery_cur1;
41529d79ce1655 Roman Li 2022-06-28 1048 unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
41529d79ce1655 Roman Li 2022-06-28 1049 unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1050
41529d79ce1655 Roman Li 2022-06-28 1051 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1052 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1053
41529d79ce1655 Roman Li 2022-06-28 1054 float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1055 float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1056 int blank_lines = 0;
41529d79ce1655 Roman Li 2022-06-28 1057
41529d79ce1655 Roman Li 2022-06-28 1058 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
41529d79ce1655 Roman Li 2022-06-28 1059 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
41529d79ce1655 Roman Li 2022-06-28 1060
41529d79ce1655 Roman Li 2022-06-28 1061 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
41529d79ce1655 Roman Li 2022-06-28 1062 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
41529d79ce1655 Roman Li 2022-06-28 1063 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en);
41529d79ce1655 Roman Li 2022-06-28 1064 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos);
41529d79ce1655 Roman Li 2022-06-28 1065 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support);
41529d79ce1655 Roman Li 2022-06-28 1066
41529d79ce1655 Roman Li 2022-06-28 1067 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz);
41529d79ce1655 Roman Li 2022-06-28 1068 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
41529d79ce1655 Roman Li 2022-06-28 1069 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz);
41529d79ce1655 Roman Li 2022-06-28 1070 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
41529d79ce1655 Roman Li 2022-06-28 1071
41529d79ce1655 Roman Li 2022-06-28 1072 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
41529d79ce1655 Roman Li 2022-06-28 1073 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
41529d79ce1655 Roman Li 2022-06-28 1074 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
41529d79ce1655 Roman Li 2022-06-28 1075
41529d79ce1655 Roman Li 2022-06-28 1076 //set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
41529d79ce1655 Roman Li 2022-06-28 1077 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1078
41529d79ce1655 Roman Li 2022-06-28 1079 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
41529d79ce1655 Roman Li 2022-06-28 1080 disp_dlg_regs->optimized_min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
41529d79ce1655 Roman Li 2022-06-28 1081 disp_dlg_regs->optimized_min_dst_y_next_start_us = 0;
41529d79ce1655 Roman Li 2022-06-28 1082 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1083 blank_lines = (dst->vblank_end + dst->vtotal_min - dst->vblank_start - dst->vstartup_start - 1);
41529d79ce1655 Roman Li 2022-06-28 1084 if (blank_lines < 0)
41529d79ce1655 Roman Li 2022-06-28 1085 blank_lines = 0;
41529d79ce1655 Roman Li 2022-06-28 1086 if (blank_lines != 0) {
41529d79ce1655 Roman Li 2022-06-28 1087 disp_dlg_regs->optimized_min_dst_y_next_start = vba__min_dst_y_next_start;
41529d79ce1655 Roman Li 2022-06-28 1088 disp_dlg_regs->optimized_min_dst_y_next_start_us = (disp_dlg_regs->optimized_min_dst_y_next_start * dst->hactive) / (unsigned int) dst->pixel_rate_mhz;
41529d79ce1655 Roman Li 2022-06-28 1089 disp_dlg_regs->min_dst_y_next_start = disp_dlg_regs->optimized_min_dst_y_next_start;
41529d79ce1655 Roman Li 2022-06-28 1090 }
41529d79ce1655 Roman Li 2022-06-28 1091 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
41529d79ce1655 Roman Li 2022-06-28 1092
41529d79ce1655 Roman Li 2022-06-28 1093 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank);
41529d79ce1655 Roman Li 2022-06-28 1094 dml_print("DML_DLG: %s: min_dst_y_next_start = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
41529d79ce1655 Roman Li 2022-06-28 1095 dml_print("DML_DLG: %s: dlg_vblank_start = 0x%0x\n", __func__, dlg_vblank_start);
41529d79ce1655 Roman Li 2022-06-28 1096 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq);
41529d79ce1655 Roman Li 2022-06-28 1097 dml_print("DML_DLG: %s: vba__min_dst_y_next_start = 0x%0x\n", __func__, vba__min_dst_y_next_start);
41529d79ce1655 Roman Li 2022-06-28 1098
41529d79ce1655 Roman Li 2022-06-28 1099 //old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
41529d79ce1655 Roman Li 2022-06-28 1100
41529d79ce1655 Roman Li 2022-06-28 1101 // -------------------------
41529d79ce1655 Roman Li 2022-06-28 1102 // Section 1.15.2.2: Prefetch, Active and TTU
41529d79ce1655 Roman Li 2022-06-28 1103 // -------------------------
41529d79ce1655 Roman Li 2022-06-28 1104 // Prefetch Calc
41529d79ce1655 Roman Li 2022-06-28 1105 // Source
41529d79ce1655 Roman Li 2022-06-28 1106 dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
41529d79ce1655 Roman Li 2022-06-28 1107 mode_422 = 0;
41529d79ce1655 Roman Li 2022-06-28 1108 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
41529d79ce1655 Roman Li 2022-06-28 1109 vp_height_l = src->viewport_height;
41529d79ce1655 Roman Li 2022-06-28 1110 vp_width_l = src->viewport_width;
41529d79ce1655 Roman Li 2022-06-28 1111 vp_height_c = src->viewport_height_c;
41529d79ce1655 Roman Li 2022-06-28 1112 vp_width_c = src->viewport_width_c;
41529d79ce1655 Roman Li 2022-06-28 1113
41529d79ce1655 Roman Li 2022-06-28 1114 // Scaling
41529d79ce1655 Roman Li 2022-06-28 1115 htaps_l = taps->htaps;
41529d79ce1655 Roman Li 2022-06-28 1116 htaps_c = taps->htaps_c;
41529d79ce1655 Roman Li 2022-06-28 1117 hratio_l = scl->hscl_ratio;
41529d79ce1655 Roman Li 2022-06-28 1118 hratio_c = scl->hscl_ratio_c;
41529d79ce1655 Roman Li 2022-06-28 1119 vratio_l = scl->vscl_ratio;
41529d79ce1655 Roman Li 2022-06-28 1120 vratio_c = scl->vscl_ratio_c;
41529d79ce1655 Roman Li 2022-06-28 1121 scl_enable = scl->scl_enable;
41529d79ce1655 Roman Li 2022-06-28 1122
41529d79ce1655 Roman Li 2022-06-28 1123 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;
41529d79ce1655 Roman Li 2022-06-28 1124 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;
41529d79ce1655 Roman Li 2022-06-28 1125 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub;
41529d79ce1655 Roman Li 2022-06-28 1126 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub;
41529d79ce1655 Roman Li 2022-06-28 1127
41529d79ce1655 Roman Li 2022-06-28 1128 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub;
41529d79ce1655 Roman Li 2022-06-28 1129 meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub;
41529d79ce1655 Roman Li 2022-06-28 1130 vupdate_offset = dst->vupdate_offset;
41529d79ce1655 Roman Li 2022-06-28 1131 vupdate_width = dst->vupdate_width;
41529d79ce1655 Roman Li 2022-06-28 1132 vready_offset = dst->vready_offset;
41529d79ce1655 Roman Li 2022-06-28 1133
41529d79ce1655 Roman Li 2022-06-28 1134 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
41529d79ce1655 Roman Li 2022-06-28 1135 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
41529d79ce1655 Roman Li 2022-06-28 1136
41529d79ce1655 Roman Li 2022-06-28 1137 if (scl_enable)
41529d79ce1655 Roman Li 2022-06-28 1138 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
41529d79ce1655 Roman Li 2022-06-28 1139 else
41529d79ce1655 Roman Li 2022-06-28 1140 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
41529d79ce1655 Roman Li 2022-06-28 1141
41529d79ce1655 Roman Li 2022-06-28 1142 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
41529d79ce1655 Roman Li 2022-06-28 1143
41529d79ce1655 Roman Li 2022-06-28 1144 if (dout->dsc_enable) {
41529d79ce1655 Roman Li 2022-06-28 1145 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
41529d79ce1655 Roman Li 2022-06-28 1146
41529d79ce1655 Roman Li 2022-06-28 1147 dispclk_delay_subtotal += dsc_delay;
41529d79ce1655 Roman Li 2022-06-28 1148 }
41529d79ce1655 Roman Li 2022-06-28 1149
41529d79ce1655 Roman Li 2022-06-28 1150 vstartup_start = dst->vstartup_start;
41529d79ce1655 Roman Li 2022-06-28 1151 if (interlaced) {
41529d79ce1655 Roman Li 2022-06-28 1152 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
41529d79ce1655 Roman Li 2022-06-28 1153 disp_dlg_regs->vready_after_vcount0 = 1;
41529d79ce1655 Roman Li 2022-06-28 1154 else
41529d79ce1655 Roman Li 2022-06-28 1155 disp_dlg_regs->vready_after_vcount0 = 0;
41529d79ce1655 Roman Li 2022-06-28 1156 } else {
41529d79ce1655 Roman Li 2022-06-28 1157 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
41529d79ce1655 Roman Li 2022-06-28 1158 disp_dlg_regs->vready_after_vcount0 = 1;
41529d79ce1655 Roman Li 2022-06-28 1159 else
41529d79ce1655 Roman Li 2022-06-28 1160 disp_dlg_regs->vready_after_vcount0 = 0;
41529d79ce1655 Roman Li 2022-06-28 1161 }
41529d79ce1655 Roman Li 2022-06-28 1162
41529d79ce1655 Roman Li 2022-06-28 1163 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
41529d79ce1655 Roman Li 2022-06-28 1164 dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0);
41529d79ce1655 Roman Li 2022-06-28 1165 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
41529d79ce1655 Roman Li 2022-06-28 1166
41529d79ce1655 Roman Li 2022-06-28 1167 if (interlaced)
41529d79ce1655 Roman Li 2022-06-28 1168 vstartup_start = vstartup_start / 2;
41529d79ce1655 Roman Li 2022-06-28 1169
41529d79ce1655 Roman Li 2022-06-28 1170 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1171 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1172
41529d79ce1655 Roman Li 2022-06-28 1173 // do some adjustment on the dst_after scaler to account for odm combine mode
41529d79ce1655 Roman Li 2022-06-28 1174 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler);
41529d79ce1655 Roman Li 2022-06-28 1175 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler);
41529d79ce1655 Roman Li 2022-06-28 1176
41529d79ce1655 Roman Li 2022-06-28 1177 // need to figure out which side of odm combine we're in
41529d79ce1655 Roman Li 2022-06-28 1178 if (dst->odm_combine) {
41529d79ce1655 Roman Li 2022-06-28 1179 // figure out which pipes go together
41529d79ce1655 Roman Li 2022-06-28 1180 bool visited[DC__NUM_PIPES__MAX];
41529d79ce1655 Roman Li 2022-06-28 1181 unsigned int i, j, k;
41529d79ce1655 Roman Li 2022-06-28 1182
41529d79ce1655 Roman Li 2022-06-28 1183 for (k = 0; k < num_pipes; ++k) {
41529d79ce1655 Roman Li 2022-06-28 1184 visited[k] = false;
41529d79ce1655 Roman Li 2022-06-28 1185 pipe_index_in_combine[k] = 0;
41529d79ce1655 Roman Li 2022-06-28 1186 }
41529d79ce1655 Roman Li 2022-06-28 1187
41529d79ce1655 Roman Li 2022-06-28 1188 for (i = 0; i < num_pipes; i++) {
41529d79ce1655 Roman Li 2022-06-28 1189 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
41529d79ce1655 Roman Li 2022-06-28 1190
41529d79ce1655 Roman Li 2022-06-28 1191 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
41529d79ce1655 Roman Li 2022-06-28 1192 unsigned int grp_idx = 0;
41529d79ce1655 Roman Li 2022-06-28 1193
41529d79ce1655 Roman Li 2022-06-28 1194 for (j = i; j < num_pipes; j++) {
41529d79ce1655 Roman Li 2022-06-28 1195 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
41529d79ce1655 Roman Li 2022-06-28 1196 pipe_index_in_combine[j] = grp_idx;
41529d79ce1655 Roman Li 2022-06-28 1197 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx);
41529d79ce1655 Roman Li 2022-06-28 1198 grp_idx++;
41529d79ce1655 Roman Li 2022-06-28 1199 visited[j] = true;
41529d79ce1655 Roman Li 2022-06-28 1200 }
41529d79ce1655 Roman Li 2022-06-28 1201 }
41529d79ce1655 Roman Li 2022-06-28 1202 }
41529d79ce1655 Roman Li 2022-06-28 1203 }
41529d79ce1655 Roman Li 2022-06-28 1204
41529d79ce1655 Roman Li 2022-06-28 1205 }
41529d79ce1655 Roman Li 2022-06-28 1206
41529d79ce1655 Roman Li 2022-06-28 1207 if (dst->odm_combine == dm_odm_combine_mode_disabled) {
41529d79ce1655 Roman Li 2022-06-28 1208 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
41529d79ce1655 Roman Li 2022-06-28 1209 } else {
41529d79ce1655 Roman Li 2022-06-28 1210 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4
41529d79ce1655 Roman Li 2022-06-28 1211 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
41529d79ce1655 Roman Li 2022-06-28 1212
41529d79ce1655 Roman Li 2022-06-28 1213 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
41529d79ce1655 Roman Li 2022-06-28 1214 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1215
41529d79ce1655 Roman Li 2022-06-28 1216 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
41529d79ce1655 Roman Li 2022-06-28 1217 dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_x_after_scaler);
41529d79ce1655 Roman Li 2022-06-28 1218 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler);
41529d79ce1655 Roman Li 2022-06-28 1219
41529d79ce1655 Roman Li 2022-06-28 1220 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1221 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1222 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1223 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1224 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1225
41529d79ce1655 Roman Li 2022-06-28 1226 max_dst_y_per_vm_vblank = 32.0; //U5.2
41529d79ce1655 Roman Li 2022-06-28 1227 max_dst_y_per_row_vblank = 16.0; //U4.2
41529d79ce1655 Roman Li 2022-06-28 1228
41529d79ce1655 Roman Li 2022-06-28 1229 // magic!
41529d79ce1655 Roman Li 2022-06-28 1230 if (htotal <= 75) {
41529d79ce1655 Roman Li 2022-06-28 1231 max_dst_y_per_vm_vblank = 100.0;
41529d79ce1655 Roman Li 2022-06-28 1232 max_dst_y_per_row_vblank = 100.0;
41529d79ce1655 Roman Li 2022-06-28 1233 }
41529d79ce1655 Roman Li 2022-06-28 1234
41529d79ce1655 Roman Li 2022-06-28 1235 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
41529d79ce1655 Roman Li 2022-06-28 1236 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip);
41529d79ce1655 Roman Li 2022-06-28 1237 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip);
41529d79ce1655 Roman Li 2022-06-28 1238 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank);
41529d79ce1655 Roman Li 2022-06-28 1239 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
41529d79ce1655 Roman Li 2022-06-28 1240
41529d79ce1655 Roman Li 2022-06-28 1241 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
41529d79ce1655 Roman Li 2022-06-28 1242
41529d79ce1655 Roman Li 2022-06-28 1243 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
41529d79ce1655 Roman Li 2022-06-28 1244
41529d79ce1655 Roman Li 2022-06-28 1245 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1246 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1247
41529d79ce1655 Roman Li 2022-06-28 1248 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1249 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1250
41529d79ce1655 Roman Li 2022-06-28 1251 // Active
41529d79ce1655 Roman Li 2022-06-28 1252 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub;
41529d79ce1655 Roman Li 2022-06-28 1253 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub;
41529d79ce1655 Roman Li 2022-06-28 1254 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height;
41529d79ce1655 Roman Li 2022-06-28 1255 meta_row_height_c = rq_dlg_param->rq_c.meta_row_height;
41529d79ce1655 Roman Li 2022-06-28 1256 swath_width_pixels_ub_l = 0;
41529d79ce1655 Roman Li 2022-06-28 1257 swath_width_pixels_ub_c = 0;
41529d79ce1655 Roman Li 2022-06-28 1258 scaler_rec_in_width_l = 0;
41529d79ce1655 Roman Li 2022-06-28 1259 scaler_rec_in_width_c = 0;
41529d79ce1655 Roman Li 2022-06-28 1260 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height;
41529d79ce1655 Roman Li 2022-06-28 1261 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height;
41529d79ce1655 Roman Li 2022-06-28 1262
41529d79ce1655 Roman Li 2022-06-28 1263 if (mode_422) {
41529d79ce1655 Roman Li 2022-06-28 1264 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element
41529d79ce1655 Roman Li 2022-06-28 1265 swath_width_pixels_ub_c = swath_width_ub_c * 2;
41529d79ce1655 Roman Li 2022-06-28 1266 } else {
41529d79ce1655 Roman Li 2022-06-28 1267 swath_width_pixels_ub_l = swath_width_ub_l * 1;
41529d79ce1655 Roman Li 2022-06-28 1268 swath_width_pixels_ub_c = swath_width_ub_c * 1;
41529d79ce1655 Roman Li 2022-06-28 1269 }
41529d79ce1655 Roman Li 2022-06-28 1270
41529d79ce1655 Roman Li 2022-06-28 1271 hscale_pixel_rate_l = 0.;
41529d79ce1655 Roman Li 2022-06-28 1272 hscale_pixel_rate_c = 0.;
41529d79ce1655 Roman Li 2022-06-28 1273 min_hratio_fact_l = 1.0;
41529d79ce1655 Roman Li 2022-06-28 1274 min_hratio_fact_c = 1.0;
41529d79ce1655 Roman Li 2022-06-28 1275
41529d79ce1655 Roman Li 2022-06-28 1276 if (hratio_l <= 1)
41529d79ce1655 Roman Li 2022-06-28 1277 min_hratio_fact_l = 2.0;
41529d79ce1655 Roman Li 2022-06-28 1278 else if (htaps_l <= 6) {
41529d79ce1655 Roman Li 2022-06-28 1279 if ((hratio_l * 2.0) > 4.0)
41529d79ce1655 Roman Li 2022-06-28 1280 min_hratio_fact_l = 4.0;
41529d79ce1655 Roman Li 2022-06-28 1281 else
41529d79ce1655 Roman Li 2022-06-28 1282 min_hratio_fact_l = hratio_l * 2.0;
41529d79ce1655 Roman Li 2022-06-28 1283 } else {
41529d79ce1655 Roman Li 2022-06-28 1284 if (hratio_l > 4.0)
41529d79ce1655 Roman Li 2022-06-28 1285 min_hratio_fact_l = 4.0;
41529d79ce1655 Roman Li 2022-06-28 1286 else
41529d79ce1655 Roman Li 2022-06-28 1287 min_hratio_fact_l = hratio_l;
41529d79ce1655 Roman Li 2022-06-28 1288 }
41529d79ce1655 Roman Li 2022-06-28 1289
41529d79ce1655 Roman Li 2022-06-28 1290 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
41529d79ce1655 Roman Li 2022-06-28 1291
41529d79ce1655 Roman Li 2022-06-28 1292 dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l);
41529d79ce1655 Roman Li 2022-06-28 1293 dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l);
41529d79ce1655 Roman Li 2022-06-28 1294 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
41529d79ce1655 Roman Li 2022-06-28 1295
41529d79ce1655 Roman Li 2022-06-28 1296 if (hratio_c <= 1)
41529d79ce1655 Roman Li 2022-06-28 1297 min_hratio_fact_c = 2.0;
41529d79ce1655 Roman Li 2022-06-28 1298 else if (htaps_c <= 6) {
41529d79ce1655 Roman Li 2022-06-28 1299 if ((hratio_c * 2.0) > 4.0)
41529d79ce1655 Roman Li 2022-06-28 1300 min_hratio_fact_c = 4.0;
41529d79ce1655 Roman Li 2022-06-28 1301 else
41529d79ce1655 Roman Li 2022-06-28 1302 min_hratio_fact_c = hratio_c * 2.0;
41529d79ce1655 Roman Li 2022-06-28 1303 } else {
41529d79ce1655 Roman Li 2022-06-28 1304 if (hratio_c > 4.0)
41529d79ce1655 Roman Li 2022-06-28 1305 min_hratio_fact_c = 4.0;
41529d79ce1655 Roman Li 2022-06-28 1306 else
41529d79ce1655 Roman Li 2022-06-28 1307 min_hratio_fact_c = hratio_c;
41529d79ce1655 Roman Li 2022-06-28 1308 }
41529d79ce1655 Roman Li 2022-06-28 1309
41529d79ce1655 Roman Li 2022-06-28 1310 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
41529d79ce1655 Roman Li 2022-06-28 1311
41529d79ce1655 Roman Li 2022-06-28 1312 refcyc_per_line_delivery_pre_l = 0.;
41529d79ce1655 Roman Li 2022-06-28 1313 refcyc_per_line_delivery_pre_c = 0.;
41529d79ce1655 Roman Li 2022-06-28 1314 refcyc_per_line_delivery_l = 0.;
41529d79ce1655 Roman Li 2022-06-28 1315 refcyc_per_line_delivery_c = 0.;
41529d79ce1655 Roman Li 2022-06-28 1316
41529d79ce1655 Roman Li 2022-06-28 1317 refcyc_per_req_delivery_pre_l = 0.;
41529d79ce1655 Roman Li 2022-06-28 1318 refcyc_per_req_delivery_pre_c = 0.;
41529d79ce1655 Roman Li 2022-06-28 1319 refcyc_per_req_delivery_l = 0.;
41529d79ce1655 Roman Li 2022-06-28 1320 refcyc_per_req_delivery_c = 0.;
41529d79ce1655 Roman Li 2022-06-28 1321
41529d79ce1655 Roman Li 2022-06-28 1322 full_recout_width = 0;
41529d79ce1655 Roman Li 2022-06-28 1323 // In ODM
41529d79ce1655 Roman Li 2022-06-28 1324 if (src->is_hsplit) {
41529d79ce1655 Roman Li 2022-06-28 1325 // This "hack" is only allowed (and valid) for MPC combine. In ODM
41529d79ce1655 Roman Li 2022-06-28 1326 // combine, you MUST specify the full_recout_width...according to Oswin
41529d79ce1655 Roman Li 2022-06-28 1327 if (dst->full_recout_width == 0 && !dst->odm_combine) {
41529d79ce1655 Roman Li 2022-06-28 1328 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__);
41529d79ce1655 Roman Li 2022-06-28 1329 full_recout_width = dst->recout_width * 2; // assume half split for dcn1
41529d79ce1655 Roman Li 2022-06-28 1330 } else
41529d79ce1655 Roman Li 2022-06-28 1331 full_recout_width = dst->full_recout_width;
41529d79ce1655 Roman Li 2022-06-28 1332 } else
41529d79ce1655 Roman Li 2022-06-28 1333 full_recout_width = dst->recout_width;
41529d79ce1655 Roman Li 2022-06-28 1334
41529d79ce1655 Roman Li 2022-06-28 1335 // As of DCN2, mpc_combine and odm_combine are mutually exclusive
41529d79ce1655 Roman Li 2022-06-28 1336 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1337 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1338 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1339 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1340 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1341 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1342 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1343 vratio_pre_l,
41529d79ce1655 Roman Li 2022-06-28 1344 hscale_pixel_rate_l,
41529d79ce1655 Roman Li 2022-06-28 1345 swath_width_pixels_ub_l,
41529d79ce1655 Roman Li 2022-06-28 1346 1); // per line
41529d79ce1655 Roman Li 2022-06-28 1347
41529d79ce1655 Roman Li 2022-06-28 1348 refcyc_per_line_delivery_l = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1349 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1350 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1351 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1352 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1353 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1354 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1355 vratio_l,
41529d79ce1655 Roman Li 2022-06-28 1356 hscale_pixel_rate_l,
41529d79ce1655 Roman Li 2022-06-28 1357 swath_width_pixels_ub_l,
41529d79ce1655 Roman Li 2022-06-28 1358 1); // per line
41529d79ce1655 Roman Li 2022-06-28 1359
41529d79ce1655 Roman Li 2022-06-28 1360 dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width);
41529d79ce1655 Roman Li 2022-06-28 1361 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
41529d79ce1655 Roman Li 2022-06-28 1362 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1363 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1364 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1365 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1366
41529d79ce1655 Roman Li 2022-06-28 1367 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1368 //old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1369
41529d79ce1655 Roman Li 2022-06-28 1370 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1371 float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1372 float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1373
41529d79ce1655 Roman Li 2022-06-28 1374 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1375 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1376 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1377 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1378 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1379 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1380 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1381 vratio_pre_c,
41529d79ce1655 Roman Li 2022-06-28 1382 hscale_pixel_rate_c,
41529d79ce1655 Roman Li 2022-06-28 1383 swath_width_pixels_ub_c,
41529d79ce1655 Roman Li 2022-06-28 1384 1); // per line
41529d79ce1655 Roman Li 2022-06-28 1385
41529d79ce1655 Roman Li 2022-06-28 1386 refcyc_per_line_delivery_c = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1387 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1388 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1389 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1390 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1391 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1392 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1393 vratio_c,
41529d79ce1655 Roman Li 2022-06-28 1394 hscale_pixel_rate_c,
41529d79ce1655 Roman Li 2022-06-28 1395 swath_width_pixels_ub_c,
41529d79ce1655 Roman Li 2022-06-28 1396 1); // per line
41529d79ce1655 Roman Li 2022-06-28 1397
41529d79ce1655 Roman Li 2022-06-28 1398 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1399 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, refcyc_per_line_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1400 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1401 dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1402
41529d79ce1655 Roman Li 2022-06-28 1403 //old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1404 //old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1405 }
41529d79ce1655 Roman Li 2022-06-28 1406
41529d79ce1655 Roman Li 2022-06-28 1407 if (src->dynamic_metadata_enable && src->gpuvm)
41529d79ce1655 Roman Li 2022-06-28 1408 disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1409
41529d79ce1655 Roman Li 2022-06-28 1410 disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1411
41529d79ce1655 Roman Li 2022-06-28 1412 // TTU - Luma / Chroma
41529d79ce1655 Roman Li 2022-06-28 1413 if (access_dir) { // vertical access
41529d79ce1655 Roman Li 2022-06-28 1414 scaler_rec_in_width_l = vp_height_l;
41529d79ce1655 Roman Li 2022-06-28 1415 scaler_rec_in_width_c = vp_height_c;
41529d79ce1655 Roman Li 2022-06-28 1416 } else {
41529d79ce1655 Roman Li 2022-06-28 1417 scaler_rec_in_width_l = vp_width_l;
41529d79ce1655 Roman Li 2022-06-28 1418 scaler_rec_in_width_c = vp_width_c;
41529d79ce1655 Roman Li 2022-06-28 1419 }
41529d79ce1655 Roman Li 2022-06-28 1420
41529d79ce1655 Roman Li 2022-06-28 1421 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1422 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1423 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1424 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1425 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1426 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1427 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1428 vratio_pre_l,
41529d79ce1655 Roman Li 2022-06-28 1429 hscale_pixel_rate_l,
41529d79ce1655 Roman Li 2022-06-28 1430 scaler_rec_in_width_l,
41529d79ce1655 Roman Li 2022-06-28 1431 req_per_swath_ub_l); // per req
41529d79ce1655 Roman Li 2022-06-28 1432
41529d79ce1655 Roman Li 2022-06-28 1433 refcyc_per_req_delivery_l = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1434 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1435 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1436 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1437 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1438 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1439 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1440 vratio_l,
41529d79ce1655 Roman Li 2022-06-28 1441 hscale_pixel_rate_l,
41529d79ce1655 Roman Li 2022-06-28 1442 scaler_rec_in_width_l,
41529d79ce1655 Roman Li 2022-06-28 1443 req_per_swath_ub_l); // per req
41529d79ce1655 Roman Li 2022-06-28 1444
41529d79ce1655 Roman Li 2022-06-28 1445 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1446 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1447 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1448 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1449
41529d79ce1655 Roman Li 2022-06-28 1450 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l);
41529d79ce1655 Roman Li 2022-06-28 1451 //old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l);
41529d79ce1655 Roman Li 2022-06-28 1452
41529d79ce1655 Roman Li 2022-06-28 1453 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1454
41529d79ce1655 Roman Li 2022-06-28 1455 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1456 float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1457 float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1458
41529d79ce1655 Roman Li 2022-06-28 1459 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1460 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1461 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1462 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1463 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1464 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1465 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1466 vratio_pre_c,
41529d79ce1655 Roman Li 2022-06-28 1467 hscale_pixel_rate_c,
41529d79ce1655 Roman Li 2022-06-28 1468 scaler_rec_in_width_c,
41529d79ce1655 Roman Li 2022-06-28 1469 req_per_swath_ub_c); // per req
41529d79ce1655 Roman Li 2022-06-28 1470 refcyc_per_req_delivery_c = get_refcyc_per_delivery(
41529d79ce1655 Roman Li 2022-06-28 1471 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1472 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1473 pclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1474 dst->odm_combine,
41529d79ce1655 Roman Li 2022-06-28 1475 full_recout_width,
41529d79ce1655 Roman Li 2022-06-28 1476 dst->hactive,
41529d79ce1655 Roman Li 2022-06-28 1477 vratio_c,
41529d79ce1655 Roman Li 2022-06-28 1478 hscale_pixel_rate_c,
41529d79ce1655 Roman Li 2022-06-28 1479 scaler_rec_in_width_c,
41529d79ce1655 Roman Li 2022-06-28 1480 req_per_swath_ub_c); // per req
41529d79ce1655 Roman Li 2022-06-28 1481
41529d79ce1655 Roman Li 2022-06-28 1482 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1483 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1484 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1485 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1486
41529d79ce1655 Roman Li 2022-06-28 1487 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c);
41529d79ce1655 Roman Li 2022-06-28 1488 //old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c);
41529d79ce1655 Roman Li 2022-06-28 1489
41529d79ce1655 Roman Li 2022-06-28 1490 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1491 }
41529d79ce1655 Roman Li 2022-06-28 1492
41529d79ce1655 Roman Li 2022-06-28 1493 // TTU - Cursor
41529d79ce1655 Roman Li 2022-06-28 1494 refcyc_per_req_delivery_pre_cur0 = 0.0;
41529d79ce1655 Roman Li 2022-06-28 1495 refcyc_per_req_delivery_cur0 = 0.0;
41529d79ce1655 Roman Li 2022-06-28 1496
41529d79ce1655 Roman Li 2022-06-28 1497 ASSERT(src->num_cursors <= 1);
41529d79ce1655 Roman Li 2022-06-28 1498
41529d79ce1655 Roman Li 2022-06-28 1499 if (src->num_cursors > 0) {
41529d79ce1655 Roman Li 2022-06-28 1500 float vba__refcyc_per_req_delivery_pre_cur0;
41529d79ce1655 Roman Li 2022-06-28 1501 float vba__refcyc_per_req_delivery_cur0;
41529d79ce1655 Roman Li 2022-06-28 1502
41529d79ce1655 Roman Li 2022-06-28 1503 calculate_ttu_cursor(
41529d79ce1655 Roman Li 2022-06-28 1504 mode_lib,
41529d79ce1655 Roman Li 2022-06-28 1505 &refcyc_per_req_delivery_pre_cur0,
41529d79ce1655 Roman Li 2022-06-28 1506 &refcyc_per_req_delivery_cur0,
41529d79ce1655 Roman Li 2022-06-28 1507 refclk_freq_in_mhz,
41529d79ce1655 Roman Li 2022-06-28 1508 ref_freq_to_pix_freq,
41529d79ce1655 Roman Li 2022-06-28 1509 hscale_pixel_rate_l,
41529d79ce1655 Roman Li 2022-06-28 1510 scl->hscl_ratio,
41529d79ce1655 Roman Li 2022-06-28 1511 vratio_pre_l,
41529d79ce1655 Roman Li 2022-06-28 1512 vratio_l,
41529d79ce1655 Roman Li 2022-06-28 1513 src->cur0_src_width,
41529d79ce1655 Roman Li 2022-06-28 1514 (enum cursor_bpp) (src->cur0_bpp));
41529d79ce1655 Roman Li 2022-06-28 1515
41529d79ce1655 Roman Li 2022-06-28 1516 vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1517 vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1518
41529d79ce1655 Roman Li 2022-06-28 1519 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0);
41529d79ce1655 Roman Li 2022-06-28 1520 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_cur0);
41529d79ce1655 Roman Li 2022-06-28 1521 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0);
41529d79ce1655 Roman Li 2022-06-28 1522 dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0);
41529d79ce1655 Roman Li 2022-06-28 1523
41529d79ce1655 Roman Li 2022-06-28 1524 //old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0);
41529d79ce1655 Roman Li 2022-06-28 1525 //old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0);
41529d79ce1655 Roman Li 2022-06-28 1526 }
41529d79ce1655 Roman Li 2022-06-28 1527
41529d79ce1655 Roman Li 2022-06-28 1528 refcyc_per_req_delivery_pre_cur1 = 0.0;
41529d79ce1655 Roman Li 2022-06-28 1529 refcyc_per_req_delivery_cur1 = 0.0;
41529d79ce1655 Roman Li 2022-06-28 1530
41529d79ce1655 Roman Li 2022-06-28 1531 // TTU - Misc
41529d79ce1655 Roman Li 2022-06-28 1532 // all hard-coded
41529d79ce1655 Roman Li 2022-06-28 1533
41529d79ce1655 Roman Li 2022-06-28 1534 // Assignment to register structures
41529d79ce1655 Roman Li 2022-06-28 1535 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
41529d79ce1655 Roman Li 2022-06-28 1536 ASSERT(disp_dlg_regs->dst_y_after_scaler < 8);
41529d79ce1655 Roman Li 2022-06-28 1537 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
41529d79ce1655 Roman Li 2022-06-28 1538 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1539 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1540 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1541 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1542 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1543 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1544
41529d79ce1655 Roman Li 2022-06-28 1545 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
41529d79ce1655 Roman Li 2022-06-28 1546 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
41529d79ce1655 Roman Li 2022-06-28 1547
41529d79ce1655 Roman Li 2022-06-28 1548 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
41529d79ce1655 Roman Li 2022-06-28 1549 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
41529d79ce1655 Roman Li 2022-06-28 1550 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
41529d79ce1655 Roman Li 2022-06-28 1551 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
41529d79ce1655 Roman Li 2022-06-28 1552
41529d79ce1655 Roman Li 2022-06-28 1553 // hack for FPGA
41529d79ce1655 Roman Li 2022-06-28 1554 if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
41529d79ce1655 Roman Li 2022-06-28 1555 if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
41529d79ce1655 Roman Li 2022-06-28 1556 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
41529d79ce1655 Roman Li 2022-06-28 1557 dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
41529d79ce1655 Roman Li 2022-06-28 1558 }
41529d79ce1655 Roman Li 2022-06-28 1559 }
41529d79ce1655 Roman Li 2022-06-28 1560
41529d79ce1655 Roman Li 2022-06-28 1561 disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
41529d79ce1655 Roman Li 2022-06-28 1562 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1563
41529d79ce1655 Roman Li 2022-06-28 1564 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1565 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
41529d79ce1655 Roman Li 2022-06-28 1566 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1567 }
41529d79ce1655 Roman Li 2022-06-28 1568
41529d79ce1655 Roman Li 2022-06-28 1569 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
41529d79ce1655 Roman Li 2022-06-28 1570 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1571
41529d79ce1655 Roman Li 2022-06-28 1572 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now
41529d79ce1655 Roman Li 2022-06-28 1573
41529d79ce1655 Roman Li 2022-06-28 1574 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
41529d79ce1655 Roman Li 2022-06-28 1575 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
41529d79ce1655 Roman Li 2022-06-28 1576
41529d79ce1655 Roman Li 2022-06-28 1577 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1578 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
41529d79ce1655 Roman Li 2022-06-28 1579 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
41529d79ce1655 Roman Li 2022-06-28 1580 }
41529d79ce1655 Roman Li 2022-06-28 1581
41529d79ce1655 Roman Li 2022-06-28 1582 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1583 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
41529d79ce1655 Roman Li 2022-06-28 1584 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1585 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
41529d79ce1655 Roman Li 2022-06-28 1586
41529d79ce1655 Roman Li 2022-06-28 1587 // Clamp to max for now
41529d79ce1655 Roman Li 2022-06-28 1588 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1589 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1590
41529d79ce1655 Roman Li 2022-06-28 1591 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1592 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1593
41529d79ce1655 Roman Li 2022-06-28 1594 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1595 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1596
41529d79ce1655 Roman Li 2022-06-28 1597 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1598 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1599
41529d79ce1655 Roman Li 2022-06-28 1600 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1601 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
41529d79ce1655 Roman Li 2022-06-28 1602 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1603 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1604 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
41529d79ce1655 Roman Li 2022-06-28 1605 dml_print(
41529d79ce1655 Roman Li 2022-06-28 1606 "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
41529d79ce1655 Roman Li 2022-06-28 1607 __func__,
41529d79ce1655 Roman Li 2022-06-28 1608 disp_dlg_regs->dst_y_per_pte_row_nom_c,
41529d79ce1655 Roman Li 2022-06-28 1609 (unsigned int) dml_pow(2, 17) - 1);
41529d79ce1655 Roman Li 2022-06-28 1610 }
41529d79ce1655 Roman Li 2022-06-28 1611 }
41529d79ce1655 Roman Li 2022-06-28 1612
41529d79ce1655 Roman Li 2022-06-28 1613 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1614 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
41529d79ce1655 Roman Li 2022-06-28 1615
41529d79ce1655 Roman Li 2022-06-28 1616 disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));
41529d79ce1655 Roman Li 2022-06-28 1617 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
41529d79ce1655 Roman Li 2022-06-28 1618
41529d79ce1655 Roman Li 2022-06-28 1619 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
41529d79ce1655 Roman Li 2022-06-28 1620 / (double) dpte_groups_per_row_ub_l);
41529d79ce1655 Roman Li 2022-06-28 1621 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1622 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1623 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
41529d79ce1655 Roman Li 2022-06-28 1624 / (double) meta_chunks_per_row_ub_l);
41529d79ce1655 Roman Li 2022-06-28 1625 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1626 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1627
41529d79ce1655 Roman Li 2022-06-28 1628 if (dual_plane) {
41529d79ce1655 Roman Li 2022-06-28 1629 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
41529d79ce1655 Roman Li 2022-06-28 1630 / (double) dpte_groups_per_row_ub_c);
41529d79ce1655 Roman Li 2022-06-28 1631 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1632 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1633
41529d79ce1655 Roman Li 2022-06-28 1634 // TODO: Is this the right calculation? Does htotal need to be halved?
41529d79ce1655 Roman Li 2022-06-28 1635 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
41529d79ce1655 Roman Li 2022-06-28 1636 / (double) meta_chunks_per_row_ub_c);
41529d79ce1655 Roman Li 2022-06-28 1637 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
41529d79ce1655 Roman Li 2022-06-28 1638 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
41529d79ce1655 Roman Li 2022-06-28 1639 }
41529d79ce1655 Roman Li 2022-06-28 1640
41529d79ce1655 Roman Li 2022-06-28 1641 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
41529d79ce1655 Roman Li 2022-06-28 1642 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
41529d79ce1655 Roman Li 2022-06-28 1643 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1644
41529d79ce1655 Roman Li 2022-06-28 1645 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
41529d79ce1655 Roman Li 2022-06-28 1646 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
41529d79ce1655 Roman Li 2022-06-28 1647 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
41529d79ce1655 Roman Li 2022-06-28 1648
41529d79ce1655 Roman Li 2022-06-28 1649 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
41529d79ce1655 Roman Li 2022-06-28 1650 disp_dlg_regs->dst_y_offset_cur0 = 0;
41529d79ce1655 Roman Li 2022-06-28 1651 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
41529d79ce1655 Roman Li 2022-06-28 1652 disp_dlg_regs->dst_y_offset_cur1 = 0;
41529d79ce1655 Roman Li 2022-06-28 1653
41529d79ce1655 Roman Li 2022-06-28 1654 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
41529d79ce1655 Roman Li 2022-06-28 1655
41529d79ce1655 Roman Li 2022-06-28 1656 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1657 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1658 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1659 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1660 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1661 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1662 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1663 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));
41529d79ce1655 Roman Li 2022-06-28 1664
41529d79ce1655 Roman Li 2022-06-28 1665 disp_ttu_regs->qos_level_low_wm = 0;
41529d79ce1655 Roman Li 2022-06-28 1666 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
41529d79ce1655 Roman Li 2022-06-28 1667
41529d79ce1655 Roman Li 2022-06-28 1668 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
41529d79ce1655 Roman Li 2022-06-28 1669 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
41529d79ce1655 Roman Li 2022-06-28 1670
41529d79ce1655 Roman Li 2022-06-28 1671 disp_ttu_regs->qos_level_flip = 14;
41529d79ce1655 Roman Li 2022-06-28 1672 disp_ttu_regs->qos_level_fixed_l = 8;
41529d79ce1655 Roman Li 2022-06-28 1673 disp_ttu_regs->qos_level_fixed_c = 8;
41529d79ce1655 Roman Li 2022-06-28 1674 disp_ttu_regs->qos_level_fixed_cur0 = 8;
41529d79ce1655 Roman Li 2022-06-28 1675 disp_ttu_regs->qos_ramp_disable_l = 0;
41529d79ce1655 Roman Li 2022-06-28 1676 disp_ttu_regs->qos_ramp_disable_c = 0;
41529d79ce1655 Roman Li 2022-06-28 1677 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
41529d79ce1655 Roman Li 2022-06-28 1678
41529d79ce1655 Roman Li 2022-06-28 1679 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
41529d79ce1655 Roman Li 2022-06-28 1680 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
41529d79ce1655 Roman Li 2022-06-28 1681
41529d79ce1655 Roman Li 2022-06-28 1682 print__ttu_regs_st(mode_lib, disp_ttu_regs);
41529d79ce1655 Roman Li 2022-06-28 1683 print__dlg_regs_st(mode_lib, disp_dlg_regs);
41529d79ce1655 Roman Li 2022-06-28 1684 }
41529d79ce1655 Roman Li 2022-06-28 1685
:::::: The code at line 1004 was first introduced by commit
:::::: 41529d79ce1655bd7463c01d9813d0abb6fb08a4 drm/amd/display: Add DCN314 DML calculation support
:::::: TO: Roman Li <roman.li@....com>
:::::: CC: Alex Deucher <alexander.deucher@....com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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