| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 6 Oct 2022 21:28:34 +0800
From: kernel test robot <lkp@...el.com>
To: Jisheng Zhang <jszhang@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: llvm@...ts.linux.dev, kbuild-all@...ts.01.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 7/8] riscv: cpu_relax: switch to
riscv_has_extension_likely()
Hi Jisheng,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.0]
[cannot apply to next-20221006]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 833477fce7a14d43ae4c07f8ddc32fa5119471a2
config: riscv-randconfig-r005-20221003
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/322e8b44d0cc6b6b2bd179469be16d70df012a1e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jisheng-Zhang/riscv-improve-boot-time-isa-extensions-handling/20221006-152055
git checkout 322e8b44d0cc6b6b2bd179469be16d70df012a1e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv prepare
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All errors (new ones prefixed by >>):
In file included from <built-in>:4:
In file included from lib/vdso/gettimeofday.c:5:
In file included from include/vdso/datapage.h:17:
In file included from include/vdso/processor.h:10:
In file included from arch/riscv/include/asm/vdso/processor.h:9:
>> arch/riscv/include/asm/hwcap.h:107:2: error: invalid operand for inline asm constraint 'i'
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
^
arch/riscv/include/asm/alternative-macros.h:187:2: note: expanded from macro 'ALTERNATIVE'
_ALTERNATIVE_CFG(old_content, new_content, vendor_id, errata_id, CONFIG_k)
^
arch/riscv/include/asm/alternative-macros.h:113:2: note: expanded from macro '_ALTERNATIVE_CFG'
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
^
arch/riscv/include/asm/alternative-macros.h:103:2: note: expanded from macro '__ALTERNATIVE_CFG'
"886 :\n" \
^
In file included from <built-in>:4:
In file included from lib/vdso/gettimeofday.c:5:
In file included from include/vdso/datapage.h:17:
In file included from include/vdso/processor.h:10:
In file included from arch/riscv/include/asm/vdso/processor.h:9:
>> arch/riscv/include/asm/hwcap.h:107:2: error: invalid operand for inline asm constraint 'i'
arch/riscv/include/asm/alternative-macros.h:187:2: note: expanded from macro 'ALTERNATIVE'
_ALTERNATIVE_CFG(old_content, new_content, vendor_id, errata_id, CONFIG_k)
^
arch/riscv/include/asm/alternative-macros.h:113:2: note: expanded from macro '_ALTERNATIVE_CFG'
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
^
arch/riscv/include/asm/alternative-macros.h:103:2: note: expanded from macro '__ALTERNATIVE_CFG'
"886 :\n" \
^
2 errors generated.
make[2]: *** [scripts/Makefile.build:250: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1
make[2]: Target 'include/generated/vdso-offsets.h' not remade because of errors.
make[1]: *** [arch/riscv/Makefile:128: vdso_prepare] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:231: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.
vim +/i +107 arch/riscv/include/asm/hwcap.h
c360cbec351103 Jisheng Zhang 2022-05-22 99
ab85f9f404c012 Jisheng Zhang 2022-10-06 100 static __always_inline bool
ab85f9f404c012 Jisheng Zhang 2022-10-06 101 riscv_has_extension_likely(const unsigned long ext)
ab85f9f404c012 Jisheng Zhang 2022-10-06 102 {
ab85f9f404c012 Jisheng Zhang 2022-10-06 103 compiletime_assert(ext < RISCV_ISA_EXT_ID_MAX,
ab85f9f404c012 Jisheng Zhang 2022-10-06 104 "ext must be < RISCV_ISA_EXT_ID_MAX");
ab85f9f404c012 Jisheng Zhang 2022-10-06 105
ab85f9f404c012 Jisheng Zhang 2022-10-06 106 asm_volatile_goto(
ab85f9f404c012 Jisheng Zhang 2022-10-06 @107 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
ab85f9f404c012 Jisheng Zhang 2022-10-06 108 :
ab85f9f404c012 Jisheng Zhang 2022-10-06 109 : [ext] "i" (ext)
ab85f9f404c012 Jisheng Zhang 2022-10-06 110 :
ab85f9f404c012 Jisheng Zhang 2022-10-06 111 : l_no);
ab85f9f404c012 Jisheng Zhang 2022-10-06 112
ab85f9f404c012 Jisheng Zhang 2022-10-06 113 return true;
ab85f9f404c012 Jisheng Zhang 2022-10-06 114 l_no:
ab85f9f404c012 Jisheng Zhang 2022-10-06 115 return false;
ab85f9f404c012 Jisheng Zhang 2022-10-06 116 }
ab85f9f404c012 Jisheng Zhang 2022-10-06 117
--
0-DAY CI Kernel Test Service
https://01.org/lkp
View attachment "config" of type "text/plain" (169668 bytes)
Powered by blists - more mailing lists